IP Library Granted Patent US 10,490,512
Granted Patent B2
US 10,490,512 · App. 16/380,990 · Granted Nov 26, 2019

Method of making plural electronic component modules

Inventors: Kenzo Kitazaki (Tokyo, JP); Takehiko Kai (Tokyo, JP); Masaya Shimamura (Tokyo, JP); Mikio Aoki (Tokyo, JP); Jin Mikata (Tokyo, JP); Taiji Ito (Tokyo, JP)
Assignee: TAIYO YUDEN CO., LTD.
H01L23/552H01L23/02H01L23/28H01L23/3121H01L25/105H01L21/561H01L2224/16225H01L2224/97H01L2924/1815
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Quick Facts
Patent No.
US 10,490,512
App. No.
16/380,990
Granted
Nov 26, 2019
Kind
B2
Abstract

A method of manufacturing a plurality of identical electronic component modules includes: preparing an assembly substrate that includes a plurality of electronic components mounted thereon; digging a first groove along the dicing lines from a top surface of a sealing member that seals each electronic component, the first groove penetrating the sealing member and reaching an intermediate depth within a base substrate; widening an upper portion of the first grove to define a second groove that is continuous with the lower portion of the first groove; forming a shielding film by depositing a film made of a conductive material on the top surface of the sealing member and on inner walls of the first and second grooves that include the sidewalls of the sealing member; and thereafter, cutting the base substrate at a bottom of the lower portion of the first groove along dicing lines.

Claims (18)

1. A method of manufacturing a plurality of identical electronic component modules, including

preparing an assembly substrate in which, in a plan view, a plurality of unit regions are defined in a matrix, boundaries between the unit regions defining dicing lines in a lattice pattern in the plan view along which the assembly substrate will be diced into the plurality of identical electronic component modules, the assembly substrate including:

a base substrate;

an electronic component mounted in each of the plurality of unit regions on the base substrate;

an electrode pattern in each of the plurality of unit regions within the base substrate; and

a sealing member made of an insulating material covering an entire surface of the base substrate including the electronic components respectively mounted in the plurality of unit regions;

digging a first groove along the dicing lines from a top surface of the sealing member, the first groove penetrating the sealing member and reaching an intermediate depth within the base substrate, a lower portion of the first groove defining and exposing a side face of the base substrate and a side face of the electrode pattern in each of the plurality of unit regions;

widening an upper portion of the first grove to define a second groove that is continuous with the lower portion of the first groove, the second groove thereby starting from the top surface of the sealing member and having a width larger than and a depth shallower than the first groove, the lower portion of the first grove and the second grove defining step-shaped sidewalls of the sealing members in each of the plurality of unit regions;

forming a shielding film by depositing, in a low-pressure atmosphere having a pressure lower than an atmospheric pressure, a film made of a conductive material on the top surface of the sealing member and on inner walls of the first and second grooves that include the sidewalls of the sealing member, the second groove providing a pathway for the conductive material to reach the inner walls of the first groove, the shielding film thereby covering the top surface of the sealing member and the inner walls of the first and second grooves and being in contact with the exposed side face of the electrode pattern in each of the plurality of unit regions; and

thereafter, separating the assembly substrate into the plurality of identical electronic component modules by cutting the base substrate at a bottom of the lower portion of the first groove along the dicing lines.

2. The method according to claim 1 , wherein the depositing of the film made of the conductive material is performed by vapor deposition, sputtering or CVD.

3. The method according to claim 1 ,

wherein the assembly substrate includes one or more vias in contact with the electrode pattern adjacent to the dicing lines in each of the plurality of unit regions,

wherein the lower portion of the first groove defines and exposes a side face of said one or more vias in each of the plurality of unit regions, and

wherein the shielding film is formed so as to be in contact with the side face of said one or more vias in each of the plurality of unit regions.

4. The method according to claim 1 ,

wherein the first groove defines and exposes a substantially horizontal portion of an electrode that is included in the base substrate at the bottom of the lower portion of the first groove in each of the plurality of unit regions, and

wherein the shielding film is formed so as to be in contact with the substantially horizontal portion of the electrode at the bottom of the lower portion of the first groove.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2022
From: TAIYO YUDEN CO., LTD.
To: KAGA FEI CO., LTD.
Reel/Frame 059769/0319 →
CHANGE OF ADDRESS Recorded Apr 29, 2022
From: TAIYO YUDEN CO., LTD.
To: TAIYO YUDEN CO., LTD.
Reel/Frame 059821/0919 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2019
From: KITAZAKI, KENZO; KAI, TAKEHIKO; SHIMAMURA, MASAYA; AOKI, MIKIO; MIKATA, JIN; ITO, TAIJI
To: TAIYO YUDEN CO., LTD.
Reel/Frame 049339/0036 →
Priority Claims (1)
JP 2017-067050 · Mar 30, 2017 · national
Continuity (2)
Division 15934829 · Mar 23, 2018
Related Publication 20190237409A1 · Aug 1, 2019