Memory device having PUC structure

1. A memory device comprising:

first and second peripheral regions in which peripheral circuits related to data input/output are disposed;

a normal cell region which is disposed on the first peripheral region, and in which a plurality of memory cells storing data are formed; and

a dummy cell region which is disposed on the second peripheral region, and in which a plurality of dummy cells forming a plurality of capacitors are formed,

wherein the dummy cell region includes: a plurality of dummy word lines extended in a first direction and arranged in a second direction; and a plurality of dummy bit lines extended in the second direction and arranged in the first direction, wherein the plurality of dummy cells are coupled between the dummy word lines and the dummy bit lines, and

wherein the plurality of dummy word lines include:

odd-numbered dummy word lines coupled to a first power supply voltage terminal; and

even-numbered dummy word lines coupled to a second power supply voltage terminal, wherein the capacitors are formed between the odd-numbered dummy word lines and the even-numbered dummy word lines.

2. The memory device of claim 1 , wherein the dummy cell region further includes:

a first coupling unit disposed on one side of the dummy word lines, and extended in the second direction to couple the odd-numbered dummy word lines to one another; and

a second coupling unit disposed on the other side of the dummy word lines, and extended in the second direction to couple the even-numbered dummy word lines to one another.

3. The memory device of claim 1 ,

wherein the plurality of dummy bit lines are coupled to the second power supply voltage terminal,

wherein the capacitors are formed between the odd-numbered dummy word lines and the dummy bit lines.

4. The memory device of claim 1 , wherein a row decoder circuit and a column decoder circuit are disposed in the first peripheral region.

5. A memory device comprising:

first and second peripheral regions in which peripheral circuits related to data input/output are disposed;

a normal cell region which is disposed on the first peripheral region, and in which a plurality of memory cells storing data are formed; and

a dummy cell region which is disposed on the second peripheral region, and in which a plurality of dummy cells forming a plurality of capacitors are formed,

wherein the dummy cell region includes: a plurality of dummy word lines extended in a first direction and arranged in a second direction; and a plurality of dummy bit lines extended in the second direction and arranged in the first direction, wherein the plurality of dummy cells are coupled between the dummy word lines and the dummy bit lines,

wherein the plurality of dummy bit lines include:

odd-numbered dummy bit lines coupled to a first power supply voltage terminal; and

even-numbered dummy bit lines coupled to a second power supply voltage terminal, and

wherein the capacitors are formed between the odd-numbered dummy bit lines and the even-numbered dummy bit lines.

6. The memory device of claim 5 , wherein the dummy cell region further includes:

a third coupling unit disposed on one side of the dummy bit lines, and extended in the first direction to couple the odd-numbered dummy bit lines to one another; and

a fourth coupling unit disposed on the other side of the dummy bit lines, and extended in the second direction to couple the even-numbered dummy bit lines to one another.

7. A memory device comprising:

first and second peripheral regions in which peripheral circuits related to data input/output are disposed;

a normal cell region which is disposed on the first peripheral region, and in which a plurality of memory cells storing data are formed; and

a dummy cell region which is disposed on the second peripheral region, and in which a plurality of dummy cells forming a plurality of capacitors are formed,

wherein the dummy cell region includes: a plurality of first dummy word lines and a plurality of second dummy word lines extended in a first direction and arranged in a second direction, and stacked in a third direction; a plurality of dummy bit lines extended in the second direction and arranged in the first direction between the first dummy word lines and the second dummy word lines disposed adjacent to each other in the third direction; a plurality of first dummy cells disposed at cross points of the first dummy word lines and the dummy bit lines, respectively; and a plurality of second dummy cells disposed at cross points of the second dummy word lines and the dummy bit lines, respectively,

wherein the plurality of first dummy word lines include:

first odd-numbered dummy word lines coupled to a first power supply voltage terminal; and

first even-numbered dummy word lines coupled to a second power supply voltage terminal, and

wherein the capacitors are formed between the first odd-numbered dummy word lines and the first even-numbered dummy word lines.

8. The memory device of claim 7 ,

wherein the plurality of second dummy word lines include:

second odd-numbered dummy word lines coupled to the second power supply voltage terminal; and

second even-numbered dummy word lines coupled to the first power supply voltage terminal,

wherein the capacitors are formed between the second odd-numbered dummy word lines and the second even-numbered dummy word lines, between the first odd-numbered dummy word lines and the second odd-numbered dummy word lines, and between the first even-numbered dummy word lines and the second even-numbered dummy word lines.

9. The memory device of claim 7 ,

wherein the plurality of dummy bit lines are coupled to the second power supply voltage terminal,

wherein the capacitors are formed between the first odd-numbered dummy word lines and the dummy bit lines.

10. A memory device comprising:

first and second peripheral regions in which peripheral circuits related to data input/output are disposed;

a normal cell region which is disposed on the first peripheral region, and in which a plurality of memory cells storing data are formed; and

a dummy cell region which is disposed on the second peripheral region, and in which a plurality of dummy cells forming a plurality of capacitors are formed,

wherein the dummy cell region includes: a plurality of first dummy word lines and a plurality of second dummy word lines extended in a first direction and arranged in a second direction, and stacked in a third direction; a plurality of dummy bit lines extended in the second direction and arranged in the first direction between the first dummy word lines and the second dummy word lines disposed adjacent to each other in the third direction; a plurality of first dummy cells disposed at cross points of the first dummy word lines and the dummy bit lines, respectively; and a plurality of second dummy cells disposed at cross points of the second dummy word lines and the dummy bit lines, respectively,

wherein the plurality of dummy bit lines include:

odd-numbered dummy bit lines coupled to a first power supply voltage terminal; and

even-numbered dummy bit lines coupled to a second power supply voltage terminal, and

wherein the capacitors are formed between the odd-numbered dummy bit lines and the even-numbered dummy bit lines.