Gate cut and fin trim isolation for advanced integrated circuit structure fabrication
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
1. A method of fabricating an integrated circuit structure, the method comprising:
forming a fin along a first direction;
forming a plurality of gate structures over the fin, individual ones of the gate structures along a second direction orthogonal to the first direction;
forming a dielectric material structure between adjacent ones of the plurality of gate structures;
removing a portion of a first of the plurality of gate structures to expose a first portion of the fin, and removing a portion of a second of the plurality of gate structures to expose a second portion of the fin, wherein the removing the portion of the first of the plurality of gate structures is performed at the same time as the removing the portion of the second of the plurality of gate structures;
subsequent to removing the portion of the first of the plurality of gate structures and removing the portion of the second of the plurality of gate structures, removing the exposed first portion of the fin but not removing the exposed second portion of the fin; and
subsequent to removing the exposed first portion of the fin but not removing the exposed second portion of the fin, forming a first insulating structure in a location of the removed first portion of the fin, and forming a second insulating structure in a location of the removed portion of the second of the plurality of gate structures, wherein the first insulating structure has a top surface co-planar with a top surface of the second insulating structure.
2. The method of claim 1 , wherein removing the portions of the first and second of the plurality of gate structures comprises using a lithographic window wider than a width of each of the portions of the first and second of the plurality of gate structures.
3. The method of claim 1 , wherein removing the exposed first portion of the fin comprises etching to a depth less than a height of the fin.
4. The method of claim 3 , wherein the depth is greater than a depth of source or drain regions in the fin.
5. The method of claim 1 , wherein the fin comprises silicon and is continuous with a portion of a silicon substrate.