Isolation structure for stacked vertical transistors
A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.
1. A method for manufacturing a semiconductor device, comprising:
forming a first vertical transistor comprising a first lower source/drain region and a first upper source/drain region on a semiconductor substrate;
forming a second vertical transistor comprising a second lower source/drain region and a second upper source/drain region stacked on the first vertical transistor;
forming an isolation layer between the first and second vertical transistors, wherein the isolation layer comprises a rare earth oxide; and
laterally etching the first and second upper and lower source/drain regions to recess lateral side surfaces of first and second upper and lower source/drain regions;
wherein the isolation layer is formed between the first upper source/drain region and the second lower source/drain region; and
wherein the isolation layer has a greater lateral width than a lateral width of the first upper source/drain region and a lateral width of the second lower source/drain region.
2. The method according to claim 1 , wherein the rare earth oxide comprises at least one of erbium oxide (Er 2 O 3 ), neodymium oxide (Nd 2 O 3 ), praseodymium oxide (Pr 2 O 3 ), cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), yttrium oxide (Y 2 O 3 ) and gadolinium oxide (Gd 2 O 3 ).
3. The method according to claim 1 , wherein the first vertical transistor comprises a first doping type and the second vertical transistor comprises a second doping type different from the first doping type.
4. The method according to claim 3 , wherein the first doping type is n-type and the second doping type is p-type.
5. The method according to claim 1 , wherein forming the first vertical transistor comprises:
forming the first lower source/drain region on the semiconductor substrate;
forming a first channel region extending vertically from the first lower source/drain region;
forming the first upper source/drain region on an upper portion of the first channel region; and
forming a first gate region around the first channel region.
6. The method according to claim 5 , wherein forming the second vertical transistor comprises:
forming the second lower source/drain region on the isolation layer;
forming a second channel region extending vertically from the second lower source/drain region;
forming the second upper source/drain region on an upper portion of the second channel region; and
forming a second gate region around the second channel region.
7. The method according to claim 6 , wherein the first gate region comprises a first gate metal layer having a first doping type, and the second gate region comprises a second gate metal layer having a second doping type different from the first doping type.
8. The method according to claim 1 , wherein forming each of the first and second vertical transistors comprises:
forming a first channel region between the first lower source/drain region and the first upper source/drain region, and forming a second channel region between the second lower source/drain region and the second upper source/drain region;
forming respective first semiconductor layers between the first lower source/drain region and the first channel region, and between the second lower source/drain region and the second channel region; and
forming respective second semiconductor layers between the first upper source/drain region and the first channel region, and between the second upper source/drain region and the second channel region.
9. The method according to claim 8 , wherein the first and second semiconductor layers comprise silicon germanium.
10. The method according to claim 8 , wherein forming each of the first and second vertical transistors further comprises:
laterally etching the first and second semiconductor layers to recess lateral side surfaces of first and second semiconductor layers with respect to lateral side surfaces of the first and second channel regions and the first and second upper and lower source/drain regions.
11. The method according claim 10 , wherein forming each of the first and second vertical transistors further comprises forming a plurality of dielectric spacers in vacant areas formed by the recessed lateral side surfaces of the first and second semiconductor layers.
12. The method according to claim 10 , wherein forming each of the first and second vertical transistors further comprises performing an annealing process to convert the first and second semiconductor layers to source/drain junction regions.
13. The method according to claim 1 , wherein forming each of the first and second vertical transistors comprises:
forming a first channel region between the first lower source/drain region and the first upper source/drain region, and forming a second channel region between the second lower source/drain region and the second upper source/drain region;
wherein the lateral side surfaces of the first and second upper and lower source/drain regions are recessed with respect to lateral side surfaces of the first and second channel regions.
14. The method according claim 13 , wherein forming each of the first and second vertical transistors further comprises forming a plurality of dielectric spacers in vacant areas formed by the recessed lateral side surfaces of the first and second upper and lower source/drain regions.
15. The method according to claim 14 , further comprising forming a dielectric liner layer on the plurality of dielectric spacers.
16. A method for manufacturing a stacked vertical transistor device, comprising:
forming a first lower source/drain region on a semiconductor substrate;
forming a first channel region extending vertically from the first lower source/drain region;
forming a first upper source/drain region on an upper portion of the first channel region;
forming a first gate region around the first channel region;
forming an isolation layer on the first upper source/drain region;
forming a second lower source/drain region on the isolation layer;
forming a second channel region extending vertically from the second lower source/drain region;
forming a second upper source/drain region on an upper portion of the second channel region;
forming a second gate region around the second channel region; and
laterally etching the first and second upper and lower source/drain regions to recess lateral side surfaces of first and second upper and lower source/drain regions;
wherein the isolation layer is formed between the first upper source/drain region and the second lower source/drain region;
wherein the isolation layer has a greater lateral width than a lateral width of the first upper source/drain region and a lateral width of the second lower source/drain region; and
wherein the isolation layer comprises a rare earth oxide.
17. The method according to claim 16 , wherein the rare earth oxide comprises at least one of erbium oxide (Er 2 O 3 ), neodymium oxide (Nd 2 O 3 ), praseodymium oxide (Pr 2 O 3 ), cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), yttrium oxide (Y 2 O 3 ) and gadolinium oxide (Gd 2 O 3 ).
18. The method according to claim 16 , wherein the first gate region comprises a first gate metal layer having a first doping type, and the second gate region comprises a second gate metal layer having a second doping type different from the first doping type.
19. The method according to claim 18 , wherein the first doping type is n-type and the second doping type is p-type.
20. The method according to claim 16 , further comprising forming a plurality of dielectric spacers in vacant areas formed by the recessed lateral side surfaces of the first and second upper and lower source/drain regions.