Qubit frequency tuning structures and fabrication methods for flip chip quantum computing devices
A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.
1. A quantum computing device, comprising:
a first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonance frequency; and
a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits, the second chip having a recess formed therein that extends through an opening in the at least one conductive surface at least to the second substrate, wherein the at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.
2. The quantum computing device of claim 1 , wherein the at least one dimension of the conductive surface is based upon a measurement of a parameter associated with each of the one or more qubits.
3. The quantum computing device of claim 2 , wherein the resonance frequency associated with a particular qubit is a predicted resonance frequency calculated based upon the measured parameter.
4. The quantum computing device of claim 2 , wherein the parameter includes a resistance associated with the one or more qubits.
5. The quantum computing device of claim 4 , wherein the resistance is a normal-state resistance of a junction of the qubit.
6. The quantum computing device of claim 5 , wherein the junction is a Josephson junction of the qubit.
7. The quantum computing device of claim 1 , wherein the at least one dimension is determined based upon a capacitance change to achieve the frequency adjustment value.
8. The quantum computing device of claim 1 , wherein the at least one dimension includes at least one of a shape or an area of the conducting surface.
9. The quantum computing device of claim 1 , wherein the frequency adjustment value is determined to mitigate a frequency collision between the resonance frequencies associated with the one or more qubits.
10. The quantum computing device of claim 1 , wherein the at least one conductive surface includes a ground plane.
11. The quantum computing device of claim 1 , wherein the at least one conductive surface is formed of at least one of a superconductive material or a metal material.
12. The quantum computing device of claim 1 , wherein the first chip and the second chip are disposed in a flip chip arrangement.
13. The quantum computing device of claim 1 , wherein the first chip and the second chip are coupled together at a predetermined distance based upon at least one of a frequency tuning range or a tuning sensitivity.
14. The quantum computing device of claim 1 , wherein the conductive surface is of at least one member selected from a set comprising Aluminum, Niobium, Titanium, Titanium Nitride, Palladium, Silver, Copper, Platinum, and Gold.
15. The quantum computing device of claim 1 , wherein the first substrate is of at least one member selected from a set comprising sapphire, silicon, quartz, gallium arsenide, fused silica, amorphous silicon, and diamond.
16. The quantum computing device of claim 1 , wherein the second substrate is of at least one member selected from a set comprising sapphire, silicon, quartz, gallium arsenide, fused silica, amorphous silicon, and diamond.
17. The quantum computing device of claim 1 , wherein the conductive surface is a superconducting material.
18. The quantum computing device of claim 1 , wherein the at least one dimension includes a depth of a recess formed in the second substrate.
19. A quantum computing device, comprising:
a first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonance frequency; and
a second chip having a second substrate and at least one conductive surface disposed on the second substrate, the at least one conductive surface defining an opening through the at least one conductive surface exposing a portion of the second substrate having a recess formed therein, wherein a depth of the recess corresponds to a desired resonance frequency associated with at least one of the one or more qubits.
20. The quantum device of claim 19 , wherein the first substrate is of at least one member selected from a set comprising sapphire, silicon, quartz, gallium arsenide, fused silica, amorphous silicon, and diamond.