Semiconductor device and method
View Patent ↗An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.
1. A device comprising:
a first fin extending from a substrate;
a first gate stack over and along sidewalls of the first fin;
a first gate spacer disposed along a sidewall of the first gate stack; and
a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region comprising:
a first epitaxial layer on the first fin, the first epitaxial layer comprising silicon and carbon;
a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin; and
a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer and the second epitaxial layer.
2. The device of claim 1 , wherein the first epitaxial layer has a uniform thickness at sides and a bottom of the first epitaxial source/drain region.
3. The device of claim 1 , wherein the first epitaxial layer is thicker at a bottom than at sides of the first epitaxial source/drain region.
4. The device of claim 1 , wherein the first epitaxial layer has an atomic concentration of carbon in a range from 0.2% to 5%.
5. The device of claim 1 , wherein the second epitaxial layer has a faceted top surface, and wherein the third epitaxial layer has a uniform thickness across the faceted top surface of the second epitaxial layer.
6. The device of claim 1 , wherein the third epitaxial layer contacts the first epitaxial layer and the first gate spacer.
7. The device of claim 1 , further comprising:
a second fin extending from the substrate;
a second gate stack over and along sidewalls of the second fin;
a second gate spacer disposed along a sidewall of the second gate stack; and
a second epitaxial source/drain region in the second fin and adjacent the second gate spacer, the second epitaxial source/drain region having a different material composition than the first epitaxial source/drain region.
8. The device of claim 1 , wherein the first epitaxial source/drain region extends under the first gate spacer.
9. A device comprising:
a fin extending upwards from a substrate;
a gate electrode over the fin; and
an epitaxial source/drain region in the fin, the epitaxial source/drain region comprising:
a first epitaxial region on the fin, the first epitaxial region comprising silicon and carbon;
a second epitaxial region on the first epitaxial region, wherein the second epitaxial region has a different material composition than the first epitaxial region, and wherein the first epitaxial region is interposed between the second epitaxial region and the fin; and
a third epitaxial region on the second epitaxial region, wherein the third epitaxial region has a different material composition than both the first epitaxial region and the second epitaxial region.
10. The device of claim 9 , wherein a ratio of a first thickness of a first sidewall of the first epitaxial region to a second thickness of a bottom of the first epitaxial region is from 0.3 to 1.3.
11. The device of claim 10 , wherein the first thickness is from 3 nm to 12 nm.
12. The device of claim 10 , wherein the second thickness is from 3 nm to 12 nm.
13. The device of claim 9 , wherein the first epitaxial region further comprises phosphorous.
14. The device of claim 9 , wherein the first epitaxial region has an atomic concentration of carbon from 0.2% to 5%.
15. A device comprising:
a semiconductor fin;
a gate stack extending on a top surface and sidewalls of the semiconductor fin;
a gate spacer extending on a sidewall of the gate stack; and
a source/drain region in the semiconductor fin and adjacent the gate spacer, the source/drain region comprising:
a first source/drain region on the semiconductor fin;
a second source/drain region on the first source/drain region, the first source/drain region separating the second source/drain region from the semiconductor fin; and
a third source/drain region on the second source/drain region, the first source/drain region having a greater concentration of carbon than the second source/drain region and the third source/drain region.
16. The device of claim 15 , wherein the semiconductor fin extends from a semiconductor substrate, wherein the first source/drain region extends below the gate spacer in a direction perpendicular with a major surface of the semiconductor substrate.
17. The device of claim 16 , wherein the first source/drain region extends laterally a distance from 0.3 nm to 5 nm under outer sidewalls of the gate spacer.
18. The device of claim 15 , further comprising a source/drain contact, the source/drain contact contacting an uppermost surface of the third source/drain region.
19. The device of claim 15 , wherein the third source/drain region has a greater concentration of phosphorous, boron, or germanium dopants than the second source/drain region.
20. The device of claim 15 , wherein the second source/drain region has a greater concentration of phosphorous, boron, or germanium dopants than the third source/drain region.