Gate driving circuit with reduced power consumption and display device including the same

1. A display device comprising:

a display panel;

a gate driving circuit comprising a plurality of stages which outputs a plurality of gate signals to the display panel based on a power signal;

a power supply circuit which generates the power signal based on a power control signal; and

a signal control circuit which outputs the power control signal,

wherein an i-th stage among the stages comprises:

a charge part which charges a charge node with a clock signal having a first high voltage for a first period;

an output part connected to the charge part through the charge node, wherein the output part charges an output node with the first high voltage of the clock signal in response to a first voltage of the charge node for the first period, and outputs a second voltage of the output node as an i-th gate signal among the gate signals;

a first discharge part connected to the output part through the output node, wherein the first discharge part discharges the second voltage to a first off voltage in response to a clock bar signal having a second high voltage for a second period following the first period; and

a second discharge part connected to the charge node, wherein the second discharge part discharges the first voltage to a second off voltage for the second period,

wherein the second off voltage has one of a first level and a second level,

wherein the first level is lower than a level of the first off voltage, and the second level is lower than the first level,

wherein i is a natural number,

wherein the clock signal swings between the first high voltage and a first low voltage during a frame,

wherein the clock bar signal swings between the second high voltage and a second low voltage during the frame,

wherein each of the first low voltage and the second low voltage has the one of the first level and the second level during the frame, and

wherein the signal control circuit outputs the power control signal to set the second off voltage to have the second level when the grayscale difference between a first frame and a second frame is equal to or greater than a first difference.

2. The display device of claim 1 , wherein the signal control circuit comprises an image analyzing unit which outputs the power control signal based on a grayscale difference between a first grayscale with respect to an image of the first frame and a second grayscale with respect to an image of the second frame following the first frame.

3. The display device of claim 2 , wherein the image analyzing unit outputs the power control signal to set the second off voltage to have the second level when the grayscale difference between the first grayscale and the second grayscale is equal to or greater than the first difference.

4. The display device of claim 2 , wherein the image analyzing unit outputs the power control signal to set the second off voltage to have the first level when the grayscale difference between the first grayscale and the second grayscale is equal to or smaller than the first difference.

5. The display device of claim 1 , wherein the power supply circuit comprises:

a power generator which outputs a gate-on voltage, the first off voltage, and the second off voltage having the second level;

a power controller which outputs the second off voltage at the first level or at the second level in response to the power control signal; and

a clock generator which generates the clock signal and the clock bar signal based on the gate-on voltage and the second off voltage output from the power controller.

6. The display device of claim 5 , wherein

the clock bar signal has the second low voltage for the first period,

the clock signal has the first low voltage for the second period, and

the clock generator sets the first low voltage and the second low voltage to have a same level as the second off voltage.

7. The display device of claim 5 , wherein the power signal comprises the clock signal, the clock bar signal, the first off voltage, and the second off voltage.

8. The display device of claim 1 , wherein the first level is between the level of the first off voltage and the second level.

9. The display device of claim 1 , wherein a first clock terminal connected to the output part is electrically connected to a first discharge terminal connected to the first discharge part through the output node.

10. The display device of claim 1 , wherein the display panel comprises:

a first substrate on which the gate driving circuit is disposed;

a second substrate disposed opposite to the first substrate; and

a liquid crystal layer disposed between the first substrate and the second substrate.