Semiconductor structure having both gate-all-around devices and planar devices

1. A method, comprising:

receiving a semiconductor substrate having a first device region and a second device region separate from the first device region;

forming a mask covering the second device region;

while the mask covers the second device region, performing:

recessing the semiconductor substrate in the first device region; and

after the recessing, epitaxially growing multiple silicon and silicon germanium layers alternately stacked in the first device region;

patterning the silicon and silicon germanium layers in the first device region to define first active regions for gate-all-around (GAA) nanowire transistors and second active regions for GAA nanosheet transistors; and

patterning the semiconductor substrate in the second device region to define third active regions for planar devices, wherein a first width of the first active regions is smaller than a second width of the second active regions, and the second width is smaller than a third width of the third active regions.

2. The method of claim 1 , wherein a distance between the first and the second device regions is at least four times a pitch of the first active regions.

3. The method of claim 1 , wherein the first width is equal to or less than 20 nm, the second width is equal to or less than 60 nm, and a ratio of the second width to the first width is in a range of 1.3 to 10.

4. The method of claim 1 , further comprising:

forming the GAA nanowire transistors using the first active regions;

forming the GAA nanosheet transistors using the second active regions; and

forming the planar devices using the third active regions.

5. The method of claim 4 , wherein the forming of the GAA nanowire transistors and the forming of the GAA nanosheet transistors includes depositing a high-k gate dielectric layer having substantially a same thickness (a first thickness) for the GAA nanowire transistors and the GAA nanosheet transistors, and wherein the forming of the planar devices includes depositing a gate dielectric layer having a second thickness greater than the first thickness.

6. The method of claim 4 , wherein the forming of the GAA nanowire transistors, the forming of the GAA nanosheet transistors, and the forming of the planar devices includes depositing a gate dielectric layer having substantially a same thickness for the GAA nanowire transistors, the GAA nanosheet transistors, and the planar devices.

7. A method, comprising:

receiving a semiconductor substrate having a first device region and a second device region separate from the first device region;

epitaxially growing multiple silicon and silicon germanium layers alternately stacked in the first and the second device regions;

forming a mask covering the first device region;

while the mask covers the first device region, performing:

recessing the silicon and silicon germanium layers in the second device region; and

after the recessing, epitaxially growing a silicon layer in the second device region;

patterning the silicon and silicon germanium layers in the first device region to define first active regions for gate-all-around (GAA) nanowire transistors and second active regions for GAA nanosheet transistors; and

patterning the silicon layer in the second device region to define third active regions for planar devices, wherein a first width of the first active regions is smaller than a second width of the second active regions that is smaller than a third width of the third active regions.

8. The method of claim 7 , further comprising:

removing the mask after the patterning of the silicon layer in the second device region.

9. The method of claim 7 , wherein the first width is equal to or less than 20 nm, the second width is equal to or less than 60 nm, a ratio of the second width to the first width is in a range of 1.3 to 10, and the third width is in a range of 60 nm to 3,000 nm.

10. The method of claim 7 , further comprising:

forming the GAA nanowire transistors using the first active regions;

forming the GAA nanosheet transistors using the second active regions; and

forming the planar devices using the third active regions.

11. The method of claim 10 , wherein the GAA nanowire transistors and the GAA nanosheet transistors are formed to have a same gate dielectric layer, and the planar devices are formed to have a thicker gate dielectric layer than the GAA nanowire transistors and the GAA nanosheet transistors.

12. A method, comprising:

receiving a semiconductor substrate having a first device region and a second device region separate from the first device region;

forming a mask covering the second device region;

while the mask covers the second device region, etching the semiconductor substrate in the first device region;

after the etching, epitaxially growing a stack of silicon and silicon germanium layers in the first device region;

patterning the stack of silicon and silicon germanium layers in the first device region to define first active regions and second active regions, wherein a first width of the first active regions is smaller than a second width of the second active regions; and

patterning the semiconductor substrate in the second device region to define third active regions.

13. The method of claim 12 , wherein the second width is smaller than a third width of the third active regions.

14. The method of claim 12 , further comprising:

forming gate-all-around (GAA) nanowire transistors in the first active regions; and

forming GAA nanosheet transistors in the second active regions.

15. The method of claim 14 , wherein the forming of the GAA nanowire transistors and the forming of the GAA nanosheet transistors includes depositing a high-k gate dielectric layer having substantially a same thickness for the GAA nanowire transistors and the GAA nanosheet transistors.

16. The method of claim 14 , further comprising:

forming planar transistors in the third active regions.

17. The method of claim 16 , wherein the planar transistors, the GAA nanowire transistors, and the GAA nanosheet transistors are formed with a gate dielectric layer having substantially a same thickness.

18. The method of claim 16 , wherein the planar transistors are formed with a gate dielectric layer that is thicker than another gate dielectric layer in one of the GAA nanowire transistors and the GAA nanosheet transistors.

19. The method of claim 12 , wherein a distance between the first device region and the second device region is at least four times a pitch between adjacent ones of the first active regions.

20. The method of claim 12 , further comprising:

forming gate-all-around (GAA) transistors in the first active regions; and

forming planar transistors in the third active regions.