Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

1. A semiconductor device, comprising:

a semiconductor body disposed above a substrate;

a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; and

sidewall spacers disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions, wherein the portion of the source and drain regions under the sidewall spacers has a width where the portion of the source and drain regions under the sidewall spacers meets the channel region, the width greater than a width of the channel region of the semiconductor body.

2. The semiconductor device of claim 1 , wherein a portion of the source and drain regions not under the sidewall spacers has a width greater than the width of the portion of the source and drain regions under the sidewall spacers.

3. The semiconductor device of claim 1 , wherein a portion of the source and drain regions not under the sidewall spacers has a width approximately the same as the width of the portion of the source and drain regions under the sidewall spacers.

4. The semiconductor device of claim 1 , wherein at least a portion of the source and drain regions is an embedded epitaxial portion of the source and drain regions.

5. The semiconductor device of claim 4 , wherein the embedded epitaxial portion of the source and drain regions comprise a semiconductor material different than the channel region.

6. The semiconductor device of claim 1 , wherein the substrate is a crystalline substrate, and the semiconductor body is continuous with the crystalline substrate.

7. The semiconductor device of claim 1 , wherein a dielectric layer is disposed between the semiconductor body and the substrate, and the semiconductor body is discontinuous with the substrate.

8. The semiconductor device of claim 1 , wherein the channel region has a width approximately in the range of 10-30 nanometers, and the width of the channel region is approximately 2-4 nanometers less than the width of the portion of the source and drain regions under the sidewall spacers.

9. The semiconductor device of claim 1 , wherein the width of the portion of the source and drain regions under the sidewall spacers is approximately 6-40% greater than the width of the channel region.

10. The semiconductor device of claim 1 , wherein the channel region is coupled to the portion of the source and drain regions under the sidewall spacers by a step feature.

11. The semiconductor device of claim 1 , wherein the channel region is coupled to the portion of the source and drain regions under the sidewall spacers by a graded feature.

12. The semiconductor device of claim 11 , wherein the graded feature comprises a facet.

13. The semiconductor device of claim 11 , wherein the graded feature comprises a rounded corner.

14. The semiconductor device of claim 11 , wherein the graded feature reduces overlap capacitance and spreading resistance during operating of the semiconductor device.

15. The semiconductor device of claim 1 , wherein the semiconductor device is disposed above the same substrate as a second semiconductor device having a channel region, and wherein the narrowest width of the channel region of the second semiconductor device is greater than the narrowest width of the channel region of the semiconductor device.

16. A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a semiconductor body disposed above a substrate;

a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; and

sidewall spacers disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions, wherein the portion of the source and drain regions under the sidewall spacers has a width where the portion of the source and drain regions under the sidewall spacers meets the channel region, the width greater than a width of the channel region of the semiconductor body.

17. The computing device of claim 16 , further comprising:

a memory coupled to the board.

18. The computing device of claim 16 , further comprising:

a communication chip coupled to the board.

19. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

20. The computing device of claim 16 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

21. A semiconductor device, comprising:

a semiconductor body disposed above a substrate;

a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; and

sidewall spacers disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions, wherein the portion of the source and drain regions under the sidewall spacers has a width greater than a width of the channel region of the semiconductor body, wherein the channel region has a width approximately in the range of 10-30 nanometers, and the width of the channel region is approximately 2-4 nanometers less than the width of the portion of the source and drain regions under the sidewall spacers.

22. A semiconductor device, comprising:

a semiconductor body disposed above a substrate;

a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; and

sidewall spacers disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions, wherein the portion of the source and drain regions under the sidewall spacers has a width greater than a width of the channel region of the semiconductor body, wherein the channel region is coupled to the portion of the source and drain regions under the sidewall spacers by a step feature.

23. A semiconductor device, comprising:

a semiconductor body disposed above a substrate;

a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; and

sidewall spacers disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions, wherein the portion of the source and drain regions under the sidewall spacers has a width greater than a width of the channel region of the semiconductor body, wherein the channel region is coupled to the portion of the source and drain regions under the sidewall spacers by a graded feature, and wherein the graded feature comprises a facet.

24. A semiconductor device, comprising:

a semiconductor body disposed above a substrate;

a gate electrode stack disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack and source and drain regions in the semiconductor body on either side of the gate electrode stack; and

sidewall spacers disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions, wherein the portion of the source and drain regions under the sidewall spacers has a width greater than a width of the channel region of the semiconductor body, wherein the semiconductor device is disposed above the same substrate as a second semiconductor device having a channel region, and wherein the narrowest width of the channel region of the second semiconductor device is greater than the narrowest width of the channel region of the semiconductor device.