IP Library › Granted Patent US 11,081,403
Granted Patent B2
US 11,081,403 · App. 16/393,543 · Granted Aug 3, 2021

Methods of forming contact features in field-effect transistors

Inventors: Yi-Hsiung Lin (Hsinchu County, TW); Yi-Hsun Chiu (Hsinchu County, TW); Shang-Wen Chang (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/823871H01L21/76224H01L21/76831H01L21/76832H01L21/823814H01L21/823821H01L21/823878H01L23/5226H01L27/0924H01L29/0847H01L29/6681H01L29/7851H01L2029/7858
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Quick Facts
Patent No.
US 11,081,403
App. No.
16/393,543
Granted
Aug 3, 2021
Kind
B2
Abstract

A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches.

Claims (44)

1. A method, comprising:

forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, wherein the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature;

forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature;

removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, wherein a top surface of a remaining portion of the dummy contact feature is above a bottommost surface of the first trench;

removing the remaining portion of the dummy contact feature to form a second trench; and

forming a metal S/D contact in the first and the second trenches.

2. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature includes selectively etching the dummy contact feature relative to the ILD layer.

3. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature exposes the first epitaxial S/D feature, such that the metal S/D contact directly contacts the first epitaxial S/D feature but not the second epitaxial S/D feature.

4. The method of claim 1 , wherein the dummy contact feature includes a dielectric material different from a dielectric material of the ILD layer.

5. The method of claim 4 , wherein the dummy contact feature includes a carbon-containing dielectric material.

6. The method of claim 1 , further comprising:

recessing a portion of the metal S/D contact to form a third trench; and

forming a dielectric material layer in the third trench, wherein a composition of the dielectric material layer is different from a composition of the ILD layer.

7. The method of claim 1 , further comprising forming a silicide layer over the first epitaxial S/D feature in the second trench before the forming of the metal S/D contact.

8. The method of claim 1 , forming the metal S/D contact includes conformally forming a barrier layer in the first trench and the second trench.

9. A method, comprising:

etching an interlayer dielectric (ILD) layer to form a first trench exposing a first source/drain (S/D) feature over a first fin, wherein the first S/D feature is disposed adjacent a second S/D feature over a second fin;

depositing a dielectric material in the first trench to form a dielectric feature; and

replacing the dielectric feature with a conductive feature, wherein the conductive feature directly contacts the first S/D feature and extends over the second S/D feature, and wherein the replacing includes:

removing a portion of the dielectric feature and a portion of the ILD layer disposed over the second S/D feature to form a second trench, wherein the removing removes the ILD layer at a greater rate than the dielectric feature, and wherein a width of the second trench spans a width of the dielectric feature and over a portion of the second S/D feature;

removing a remaining portion of the dielectric feature to form a third trench that exposes the first S/D feature; and

forming the conductive feature in the second and the third trench.

10. The method of claim 9 , the ILD layer being a first ILD layer, the method further comprising, before the etching of the first ILD layer:

forming an etch-stop layer over the first ILD layer; and

forming a second ILD layer over the etch-stop layer.

11. The method of claim 10 , wherein forming the second trench includes removing a portion of the second ILD layer disposed above the etch-stop layer.

12. The method of claim 10 , wherein forming the second trench is stopped by the etch-stop layer.

13. The method of claim 9 , wherein forming the conductive feature includes:

depositing a conductive material in the second trench and the third trench; and

planarizing a top surface of the conductive material to form the conductive feature.

14. The method of claim 13 , further comprising conformally forming a barrier layer in the third trench before the depositing of the conductive material.

15. The method of claim 9 , wherein removing the portion of the dielectric feature and the portion of the ILD layer includes forming a patterned resist layer over the portion of the dielectric feature and the portion of the ILD layer, and wherein removing the remaining portion of the dielectric feature includes selectively etching the dielectric feature relative to the ILD layer.

16. A method, comprising:

forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, wherein the first epitaxial S/D feature is disposed over a first fin and the second epitaxial S/D feature is disposed over a second fin oriented parallel to the first fin;

forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature;

performing a first etching process to remove a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature, thereby forming a first trench, wherein outermost sidewalls and a bottommost surface of the first trench are defined by the ILD layer;

performing a second etching process to selectively remove a remaining portion of the dummy contact feature with respect to the ILD layer, thereby forming a second trench that exposes the first epitaxial S/D feature; and

forming a metal S/D contact in the first and the second trenches, wherein the metal S/D contact is fully embedded in the ILD layer.

17. The method of claim 16 , wherein performing the first etching process removes the ILD layer at a greater rate than the dummy contact feature, and wherein performing the second etching process removes the dummy contact feature at a greater etching rate than the ILD layer.

18. The method of claim 16 , wherein the first etching process is performed using a patterned masking element, and wherein the second etching process is performed without using a patterned masking element.

19. The method of claim 16 , wherein the metal S/D contact includes a first portion electrically coupled with the first epitaxial S/D feature and a second portion suspended above the second epitaxial S/D feature, such that the metal S/D contact is configured to electrically connect the first epitaxial S/D feature with a third epitaxial S/D feature disposed over the second fin and adjacent to the second epitaxial S/D feature.

20. The method of claim 16 , further comprising:

removing a top portion of the metal S/D contact to form a third trench; and

forming a dielectric layer in the third trench.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2019
From: LIN, YI-HSIUNG; CHIU, YI-HSUN; CHANG, SHANG-WEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 050229/0334 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2019
From: LIN, YI-HSIUNG; CHIU, YI-HSUN; CHANG, SHANG-WEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 050334/0607 →
Continuity (2)
Provisional Application 62691800 · Jun 29, 2018
Related Publication 20200006160A1 · Jan 2, 2020
Cited By (2)
US 12,628,404 US 12,653,007