IP Library › Granted Patent US 10,937,688
Granted Patent B2
US 10,937,688 · App. 16/396,793 · Granted Mar 2, 2021

Semiconductor package and method of fabricating semiconductor package

Inventors: Zi-Jheng Liu (Taoyuan, TW); Chen-Cheng Kuo (Shin-Chu County, TW); Hung-Jui Kuo (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/76807H01L21/02645H01L21/56H01L21/78H01L23/3114H01L23/5329H01L23/5384H01L24/32H01L2221/1015H01L2224/0231H01L2224/32225H01L2924/14
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Quick Facts
Patent No.
US 10,937,688
App. No.
16/396,793
Granted
Mar 2, 2021
Kind
B2
Abstract

A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

Claims (26)

1. A method of forming a semiconductor structure, comprising

providing a substrate having at least one contact therein and a dielectric material layer thereon;

performing a double exposure process to the dielectric material layer including sequentially performing a first exposure process to form first exposure portions in the dielectric material layer and performing a second exposure process to form second exposure portions in the dielectric material layer;

performing a development process to dissolve the first and second exposure portions and over-develop the dielectric material layer to form a dual damascene opening with a via opening wider than the first exposure portions and a trench opening wider than the second exposure portion;

forming a seed metallic layer over the dual damascene opening and over the dielectric material layer; and

forming a metallic pattern filled in the dual damascene opening and electrically connected with the at least one contact.

2. The method as claimed in claim 1 , wherein the first exposure portions are formed with a first depth in the dielectric material layer and the second exposure portions are formed with a second depth in the dielectric material layer, and the first depth is larger than the second depth.

3. The method as claimed in claim 2 , wherein locations of the first exposure portions are overlapped with locations of the second exposure portions.

4. The method as claimed in claim 1 , wherein the first exposure process is performed with a first energy dose and the second exposure process is performed with a second energy dose, and the first energy dose is larger than the second energy dose.

5. The method as claimed in claim 1 , wherein the via opening exposes the at least one contact and the trench opening is connected with the at least one via opening.

6. The method as claimed in claim 5 , wherein forming a metallic pattern in the dual damascene opening includes forming a via portion located within the via opening and forming a routing portion located within the trench opening.

7. The method as claimed in claim 1 , wherein forming a metallic pattern comprises forming a metallic layer filling the dual damascene opening, and performing a planarization process to remove the metallic layer and the seed metallic layer outside the dual damascene opening.

8. A method of forming an interconnection structure, comprising:

providing a substrate having contacts and a dielectric material layer covering the contacts;

performing a first exposure process with a first energy dose to form first exposure portions in the dielectric material layer;

performing a second exposure process with a second energy dose to form second exposure portions in the dielectric material layer, wherein the first energy dose is larger than the second energy dose;

performing a development process dissolving the first exposure portions and the second exposure portions of the dielectric material layer and over-developing the dielectric material layer in the same development process to form via openings larger than the first exposure portions and the trench openings larger than the second exposure portions;

forming a seed metallic layer over the dielectric material layer and covering the via openings and trench openings; and

forming metal patterns on the seed metallic layer and filled within the via openings and the trench openings.

9. The method as claimed in claim 8 , wherein performing the development process further comprises performing a curing process.

10. The method as claimed in claim 8 , wherein the seed metallic layer is formed conformally covering the via openings and the trench openings.

11. The method as claimed in claim 10 , wherein the seed metallic layer including titanium and copper is formed by sputtering.

12. The method as claimed in claim 10 , wherein the seed metallic layer is formed to cover the contacts exposed by the via openings.

13. The method as claimed in claim 8 , wherein forming metal patterns comprises forming a metal layer filling the via openings and the trench openings, and performing a planarization process to remove the metal layer and the seed metallic layer outside the dual damascene opening.

14. The method as claimed in claim 13 , wherein the metal layer including copper is formed by electroplating.

15. The method as claimed in claim 8 , wherein the first exposure portions are formed at locations overlapped with locations of the second exposure portions.

Continuity (2)
Continuation 15688817 · Aug 28, 2017
Related Publication 20190295884A1 · Sep 26, 2019