Multi-bit memory system with adaptive read voltage controller

1. A memory system comprising:

a semiconductor memory including a first word line and a first memory cell coupled to the first word line, the first memory cell being capable of holding multi bit data including, a first bit and a second bit; and

a controller capable of issuing a first command and a second command, wherein

in response to the issued first command, the semiconductor memory executes a first reading operation, the first reading operation including applying a voltage within a first range and a voltage within a second range to the first word line and reading the first bit from the first memory cell,

in response to the issued second command, the semiconductor memory executes a second reading operation, the second reading operation applying a voltage between the first range and the second range to the first word line and reading a third bit from the first memory cell,

the controller issues the first command a plurality of times and changes the voltage within the first range and the voltage within the second range in accordance with the plurality of first commands, and

the controller specifies a first voltage within the first range based on a first bit count generated based on at least the read first bits and the third bit, each of the read first bits corresponding to each of the plurality of first commands.

2. The memory system of claim 1 , wherein

the semiconductor memory generates each of a plurality of fourth bits based on at least each of the read first bits and the third bit, each of the plurality of fourth bits corresponding to each of the read first bits, and

the controller generates the first bit count based on the plurality of fourth bits.

3. The memory system of claim 1 , wherein

the semiconductor memory generates each of a plurality of fifth bits based on at least each of the read first bits and the third bit, each of the plurality of fifth bits corresponding to each of the read first bits, and

the controller generates a second bit count, based on the plurality of fifth bits and specifies a second voltage within the second a e based on the second bit count.

4. The memory system of claim 3 , wherein

the controller estimates a third voltage within a third range based on a difference between the first voltage and the second voltage, the third range being different from the first range and the second range,

the controller is capable of issuing a third command, and

in response to the issued third command, the semiconductor memory applies the third voltage to the first word line and reads the second bit from the first memory cell.

5. The memory system of claim 4 , wherein

the controller estimates a third voltage within a third range based on an inter mediate voltage between the first voltage and the second voltage, the third range being different from the first range and the second range,

the controller is capable of issuing a third command, and

in response to the issued third command, the semiconductor memory applies the third voltage to the first word line and reads the second bit from the first memory cell.

6. The memory system of claim 1 , wherein

the controller estimates a third voltage within a third range based on at least the first voltage, the third range being different from the first range and the second range,

the controller is capable of issuing a third command, and

in response to the issued third command, the semiconductor memory applies the third voltage to the first word line and reads the second bit from the first memory cell.

7. The memory system of claim 6 , wherein the controller estimates the third voltage based on a difference between the first voltage and a fourth voltage within the first range.

8. The memory system of claim 6 , wherein

the semiconductor memory further includes a second word line and a second memory cell coupled to the second word line,

the first memory cell and the second memory cell are connected in series, and

in response to the issued third command, the semiconductor memory applies, to the second word line, a fourth voltage and a fifth voltage during which the third voltage is applied to the first word line, the fifth voltage being different from the fourth voltage.

9. The memory system of claim 8 , wherein

the semiconductor memory sequentially applies to the second word line, the fourth voltage and the fifth voltage, and

the fifth voltage is higher than the fourth voltage.

10. The memory system of claim 1 , wherein

the semiconductor memory further includes a second word line and a second memory cell coupled to the second word line, the second memory cell being capable of holding multi bit data including the first bit and the second bit, and

the first memory cell and the second memory cell are connected in series, and

in response to the issued first command, the semiconductor memory applies, to the second word line, a fourth voltage and a fifth voltage during which the voltage within the first range is applied to the first word line, the fifth voltage being different from the fourth voltage.

11. The memory system of claim 10 , wherein

the semiconductor memory sequentially applies to the second word line, the fourth voltage and the fifth voltage, and

the fifth voltage is larger than the fourth voltage.

12. The memory system of claim 1 , wherein

the number of the plurality of times is at least four times,

the voltage within the first range in a second time of the plurality of times is lower than the voltage within the first range in a first time of the plurality of times,

the voltage within the first range in a third time of the plurality of times is lower than the voltage within the first range in the second time of the plurality of times,

the voltage within the second range in the second time of the plurality of times is lower than the voltage within the second range in the first time of the plurality of times, and

the voltage within the second range in the third time of the plurality of times is lower than the voltage within the second range in the second time of the plurality of times.

13. The memory system of claim 1 , wherein

the first reading operation includes further applying a voltage within a third range to the first word line,

the controller is capable of issuing further a fourth command,

in response to the issued fourth command, the semiconductor memory executes a third reading operation, the third reading operation applying a voltage within between the second range and the third range to the first word line and reads a sixth bit from the first memory cell,

the first bit count is generated based on the read first bits, the third bit and the sixth bit, and

the controller specifies the first voltage based on the generated first bit count.

14. The memory system of claim 13 , wherein

the semiconductor memory generates each of a plurality of fourth bits based on each of the read bits, the third bit, and the sixth bit, each of the plurality of fourth bits corresponding to each of the read first bits, and

the controller generates the first bit count based on the plurality of fourth bits.

15. The memory system of claim 14 , wherein

the semiconductor memory further includes a first latch, a second latch, and a third latch,

the semiconductor memory stores the third bit in the first latch, stores the sixth bit in the second latch, and stores one of the read first bits in the third latch,

the semiconductor memory generates one of the plurality of fourth bits based on the third bit in the first latch, the sixth bit in the second latch, and the one of the read first bits in the third latch, and

the semiconductor memory sends each of the plurality of the fourth bits to the controller.