Method for manufacturing a semiconductor device
According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
1. A semiconductor device comprising:
a co-catalyst layer above a surface of a semiconductor substrate, the co-catalyst layer comprising a face-centered cubic structure or a hexagonal close-packed structure, or an amorphous structure or a microcrystalline structure, wherein the co-catalyst layer is configured such that a (111) face of the face-centered cubic structure or a (002) face of the hexagonal close-packed structure is to be oriented parallel to the surface of the semiconductor when the co-catalyst layer comprises the face-centered cubic structure or the hexagonal close-packed structure;
a catalyst layer on the co-catalyst layer, the catalyst layer comprising a face-centered cubic structure or a hexagonal close-packed structure, or an amorphous structure or a microcrystalline structure, wherein the catalyst layer is configured such that a (111) face of the face-centered cubic structure or a (002) face of the hexagonal close-packed structure is to be oriented parallel to the surface of the semiconductor when the catalyst layer comprises the face-centered cubic structure or the hexagonal close-packed structure; and
a graphene layer on the catalyst layer,
wherein the catalyst layer further comprises a multilayer structure in which a first material layer and a second material layer are alternately stacked, the first material layer includes a first material as a catalyst, the second material layer includes a second material having a melting point higher than that of the first material, and the second material forms a eutectic with the first material, or the second material forms complete soluble with the first material.
2. The device of claim 1 , wherein the first material is one selected from a group consisting of Ni, Co, and Fe, or a nitride of the material selected from the group, or an alloy including at least two materials selected from the group.
3. The device of claim 2 , wherein the first material is Ni, the second material is Cr, Tc, Ru, Os, Re, or C when the second material forms the eutectic with the first material, and the second material is Pd, Pt, Rh, or Ir when the second material forms the complete soluble with the first material.
4. The device of claim 2 , wherein the first material is Co, the second material is C when the second material forms the eutectic with the first material, and the second material is Pd, Pt, Rh, Ru, Ir, Os, or Re when the second material forms the complete soluble with the first material.
5. The device of claim 2 , wherein the first material is Fe, the second material is Ru, Cd, or C when the second material forms the eutectic with the first material, and the second material is Cr, Pt, Rh, Ir, or W when the second material forms the complete soluble with the first material.
6. The device of claim 1 , wherein the catalyst layer is a laminated film doped with the second material, and the laminated film includes films made of different materials selected from a group consisting of Ni, nitride of Ni, Co, nitride of Co, Fe, and nitride of Fe.
7. The device of claim 1 , wherein the co-catalyst layer comprises the second material.
8. The device of claim 1 , wherein the graphene layer, the catalyst layer, and the co-catalyst layer constitute a wiring.
9. The device of claim 1 , further comprising a protective film on the graphene layer.