IP Library Granted Patent US 11,037,799
Granted Patent B2
US 11,037,799 · App. 16/400,620 · Granted Jun 15, 2021

Metal heterojunction structure with capping metal layer

Inventors: Yi-Sheng Lin (Taichung, TW); Chi-Jen Liu (Taipei, TW); Kei-Wei Chen (Tainan, TW); Liang-Guang Chen (Hsinchu, TW); Te-Ming Kung (Taichung, TW); William Weilun Hong (Hsinchu, TW); Chi-Hsiang Shen (Tainan, TW); Chia-Wei Ho (Kaohsiung, TW); Chun-Wei Hsu (Hsinchu, TW); Yang-Chun Cheng (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
H01L21/3212H01L21/7684H01L21/76805H01L21/76816H01L21/76849H01L21/76895H01L23/5283H01L23/535H01L23/53209H01L23/53228H01L23/53257C09G1/02
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Quick Facts
Patent No.
US 11,037,799
App. No.
16/400,620
Granted
Jun 15, 2021
Kind
B2
Abstract

The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Claims (36)

1. A semiconductor structure, comprising:

a substrate;

a semiconductor device over the substrate;

a first interconnect structure within a first dielectric layer and connecting to a terminal of the semiconductor device;

a first cap structure over the first interconnect structure and contacting the first interconnect structure, the first cap structure at least partially within the first dielectric layer and adjacent to an upper portion of the first dielectric layer, the upper portion of the first dielectric layer including an ion implantation different from a lower portion of the first dielectric layer that is closer to the substrate than the upper portion of the first dielectric layer; and

a second interconnect structure over the first cap structure and contacting the first cap structure.

2. The semiconductor structure of claim 1 , wherein the upper portion of the first dielectric layer includes a tensile stress against an interface between the first dielectric layer and the first cap structure.

3. The semiconductor structure of claim 1 , wherein the first cap structure is at least partially within the upper portion of the first dielectric layer.

4. The semiconductor structure of claim 1 , wherein the ion implantation in the upper portion of the first dielectric layer includes one or more of germanium, silicon, carbon, nitrogen, phosphorus or boron.

5. The semiconductor structure of claim 1 , wherein the first cap structure includes a same conductive material as the second interconnect structure.

6. The semiconductor structure of claim 1 , wherein the first cap structure includes a different conductive material from the first interconnect structure.

7. The semiconductor structure of claim 6 , wherein a conductive material of the first cap structure is different from a conductive material of the first interconnect structure in reacting to at least one of an acidic solution or an alkaline solution.

8. The semiconductor structure of claim 6 , wherein one of the first cap structure or the first interconnect structure is tungsten and another one of the first cap structure or the first interconnect structure is one or more of cobalt or copper.

9. The semiconductor structure of claim 1 , wherein the first cap structure extends laterally beyond the second interconnect structure at least in one direction.

10. The semiconductor structure of claim 1 , wherein the first cap structure includes a different diameter than the second interconnect structure.

11. The semiconductor structure of claim 1 , wherein the first cap structure misaligns with the second interconnect structure.

12. The semiconductor structure of claim 1 , further comprising a second cap structure directly over the second interconnect structure and a third interconnect structure directly over the second cap structure.

13. A semiconductor structure, comprising:

a substrate;

a dielectric layer over the substrate, the dielectric layer including an upper portion and a lower portion that is closer to the substrate than the upper portion, the upper portion including an ion implantation different from the lower portion and having a tensile stress due to the ion implantation;

an conductive via structure within the dielectric layer, an upper surface of the conductive via structure being lower than an upper surface of the dielectric layer adjacent to the conductive via structure; and

a conductive cap structure directly over the conductive via structure, an upper surface of the conductive cap structure being one of substantially at a same level with or higher than the upper surface of the dielectric layer adjacent to the conductive via structure.

14. The semiconductor structure of claim 13 , wherein the conductive cap structure extends laterally beyond the conductive via structure at least in one direction.

15. The semiconductor structure of claim 13 , wherein the conductive cap structure misaligns with the conductive via structure.

16. A structure, comprising:

a substrate;

a first dielectric layer over the substrate, the dielectric layer including an upper portion and a lower portion that is closer to the substrate than the upper portion, the upper portion including an ion implantation different from the lower portion;

a first metal structure within the first dielectric layer, an upper surface of the first metal structure being lower than an upper surface of the first dielectric layer that is adjacent to the upper surface of the first metal structure; and

a second metal structure over the upper surface of the first metal structure, the second metal structure adjacent to the upper portion of the first dielectric layer;

wherein the upper portion of the first dielectric layer includes a tensile stress against an interface between the first dielectric layer and the second metal structure.

17. The structure of claim 16 , wherein the upper portion of the first dielectric layer includes implanted ions of one or more of germanium, silicon, carbon, nitrogen, phosphorus or boron.

18. The structure of claim 16 , further comprising:

a third metal structure directly over the second metal structure; and

a second dielectric layer over the first dielectric layer and surrounding the third metal structure.

19. The structure of claim 16 , wherein the second metal structure includes a different conductive material from the first metal structure.

20. The structure of claim 19 , wherein a conductive material of the second metal structure is different from a conductive material of the first metal structure in reacting to at least one of an acidic solution or an alkaline solution.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2019
From: LIN, YI-SHENG; LIU, CHI-JEN; SHEN, CHI-HSIANG; KUNG, TE-MING; HSU, CHUN-WEI; HO, CHIA-WEI; CHENG, YANG-CHUN; HONG, WILLIAM WEILUN; CHEN, LIANG-GUANG; CHEN, KEI-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 050760/0219 →
Continuity (2)
Provisional Application 62736957 · Sep 26, 2018
Related Publication 20200098591A1 · Mar 26, 2020