Performance monitoring of design-based alignment
Alignment can be monitored by positioning at least one alignment verification location per alignment frame. The alignment verification location is a coordinate within the alignment frame. A distance between each of the alignment verification locations and a closest instance of an alignment target is determined. An alignment score can be determined based on the distance. The alignment score can include a number of the alignment frames between the alignment verification location and the alignment target. If the alignment score is below a threshold, then alignment setup can be performed.
1. A system comprising:
a light source that directs a light beam at a wafer;
a stage configured to hold the wafer;
a detector that receives the light beam reflected off the wafer; and
a processor in electronic communication with the detector, wherein the processor is configured to:
position at least one alignment verification location per alignment frame of an image of the wafer, wherein the alignment verification location is a coordinate within the alignment frame;
determine a distance between each of the alignment verification locations and a closest instance of an alignment target; and
determine an alignment score based on the distance, wherein the alignment score includes a number of the alignment frames between the alignment verification location and the alignment target.
2. The system of claim 1 , wherein the processor is configured to inspect the wafer and report defects if the alignment score is above a threshold.
3. The system of claim 1 , wherein the processor is configured to perform alignment setup if the alignment score is below a threshold.
4. The system of claim 1 , wherein the alignment score is determined for a care area in the alignment frame.
5. The system of claim 1 , wherein the alignment frame is from 5 μm 2 to 10 μm 2 .
6. The system of claim 1 , wherein the processor is configured to determine a map of alignment scores for the wafer.
7. A method comprising:
positioning, using a processor, at least one alignment verification location per alignment frame on at least one image of a wafer, wherein the alignment verification location is a coordinate within the alignment frame;
determining, using the processor, a distance between each of the alignment verification locations and a closest instance of an alignment target; and
determining, using the processor, an alignment score based on the distance, wherein the alignment score includes a number of the alignment frames between the alignment verification location and the alignment target.
8. The method of claim 7 , wherein the alignment target is a device or pattern in the alignment frame.
9. The method of claim 7 , further comprising inspecting the wafer and reporting defects if the alignment score is above a threshold.
10. The method of claim 7 , further comprising performing alignment setup if the alignment score is below a threshold.
11. The method of claim 7 , wherein the alignment score is determined for a care area in the alignment frame.
12. The method of claim 7 , wherein the alignment frame is from 5 μm 2 to 10 μm 2 .
13. The method of claim 7 , further comprising determining a map of alignment scores for the wafer using the processor.
14. A non-transitory computer-readable storage medium, comprising one or more programs for executing the following steps on one or more computing devices:
positioning at least one alignment verification location per alignment frame on at least one image of a wafer, wherein the alignment verification location is a coordinate within the alignment frame;
determining a distance between each of the alignment verification locations and a closest instance of an alignment target; and
determining an alignment score based on the distance, wherein the alignment score includes a number of the alignment frames between the alignment verification location and the alignment target.
15. The non-transitory computer-readable storage medium of claim 14 , wherein the programs further inspect the wafer and report defects if the alignment score is above a threshold.
16. The non-transitory computer-readable storage medium of claim 14 , wherein the programs further perform alignment setup if the alignment score is below a threshold.
17. The non-transitory computer-readable storage medium of claim 14 , wherein the alignment score is determined for a care area in the alignment frame.
18. The non-transitory computer-readable storage medium of claim 14 , wherein the alignment frame is from 5 μm 2 to 10 μm 2 .
19. The non-transitory computer-readable storage medium of claim 14 , wherein the programs further determine a map of alignment scores for the wafer using the processor.