Modular and dynamic digital control in a quantum controller
View Patent ↗A quantum controller comprises a quantum control pulse generation circuit and digital signal management circuit. The quantum control pulse generation circuit is operable to generate a quantum control pulse which can be processed by any of a plurality of controlled circuits, and generate a first digital signal which can be routed to any of the plurality of controlled circuits. The digital signal management circuit is operable to detect, during runtime, to which one or more of the plurality of controlled circuits the first digital signal is to be routed, to manipulate the first digital signal based on the one or more of the plurality of controlled circuits to which the first digital signal is to be routed, where the manipulation results in one or more manipulated digital signals, and to route the one or more manipulated digital signals to one or more of the plurality of controlled circuits.
1. A system comprising:
a quantum control pulse generation circuit operable to:
generate a quantum control pulse which can be processed by any of a plurality of controlled circuits; and
generate a first digital signal which can be routed to any of the plurality of controlled circuits; and
a digital signal management circuit operable to:
detect, during runtime, to which one or more of the plurality of controlled circuits the first digital signal is to be routed;
manipulate the first digital signal based on the one or more of the plurality of controlled circuits to which the first digital signal is to be routed, wherein the manipulation results in one or more manipulated digital signals; and
route the one or more manipulated digital signals to one or more of the plurality of controlled circuits.
2. The system of claim 1 , wherein, for each of the one or more manipulated digital signals, the manipulation comprises a delay of the first digital signal by an amount of time determined based on a propagation time of the quantum control pulse from the quantum control pulse generation circuit to one of the plurality of controlled circuits.
3. The system of claim 2 , wherein the digital signal management circuit is operable to:
delay a first of the one or more manipulated digital signals intended for a first of the plurality of controlled circuits by a first amount of time; and
delay a second of the one or more manipulated digital signals intended for a second of the plurality of controlled circuits by a second amount of time.
4. The system of claim 1 , wherein, for each of the one or more manipulated digital signals, the manipulation comprises a convolution of the first digital signal by a digital bit pattern.
5. The system of claim 4 , wherein the digital signal management circuit is operable to select the digital bit pattern from a plurality of digital bit patterns based on the one or more of the plurality of controlled circuits to which the first digital signal is to be routed.
6. The system of claim 5 , wherein the digital signal management circuit is operable to:
convolve the first digital signal with a first digital bit pattern of the plurality of digital bit patterns to generate a first one of the one or more manipulated digital signals; and
convolve the first digital signal with a second digital bit pattern of the plurality of digital bit patterns to generate a second one of the one or more manipulated digital signals.
7. The system of claim 1 , wherein:
The plurality of controlled circuits comprise a gating circuit which;
when the gating circuit is closed, the quantum control pulse is permitted to propagate to a destination;
when the gating circuit is open, the quantum control pulse is prevented from propagating to the destination; and
one of the one or more manipulated digital signals controls whether the gating circuit is closed or open.
8. The system of claim 7 , wherein the destination is a quantum processor.
9. The system of claim 7 , wherein:
the gating circuit is part of an input manager circuit configured to receive a return of the quantum control pulse from a quantum processor; and
the destination is a quantum control pulse generation circuit.
10. The system of claim 1 , wherein:
the quantum control pulse generation circuit is operable to generate a second digital signal; and
the detection of to which one or more of the plurality of controlled circuits the first digital signal is to be routed is based on the second digital signal.
11. The system of claim 10 , wherein:
the second digital signal is a multi-bit signal;
a state of each bit of the second digital signal determines whether the first digital signal is to be routed to a respective one of the plurality of controlled circuits.
12. The system of claim 1 , wherein:
the digital signal management circuit comprises a first processing path configured to manipulate the first digital signal to generate a first one of the one or more manipulated digital signals to be routed to a first one of the plurality of controlled circuits; and
the digital signal management circuit comprises a second processing path configured to manipulate the first digital signal to generate a second one of the one or more manipulated digital signals to be routed to a second one of the plurality of controlled circuits.
13. The system of claim 12 , wherein:
the first processing path is configured to introduce a first delay to the first digital signal;
the second processing path is configured to introduce a second delay to the first digital signal; and
the first delay is different than the second delay.
14. The system of claim 12 , wherein:
the first processing path is configured to convolve the first digital signal with a first bit pattern;
the second processing path is configured to convolve the first digital signal with a second bit pattern; and
the first bit pattern is different than the second bit pattern.
15. The system of claim 12 , wherein:
the quantum control pulse generation circuit is operable to generate a second digital signal; and
the digital signal management circuit is operable to select to which of the first processing path and the second processing path to route the first digital signal based on the second digital signal.
16. The system of claim 15 , wherein:
the second digital signal comprises a first bit and a second bit;
a state of the first bit of the second digital signal determines whether the first digital signal is to be processed by the first processing path; and
a state of the second bit of the second digital signal determines whether the first digital signal is to be processed by the second processing path.
17. The system of claim 1 , wherein:
the plurality of controlled circuits comprise a switch; and
one of the one or more manipulated digital signals controls the switch.
18. The system of claim 1 , wherein:
the plurality of controlled circuits comprise a measurement device; and
one of the one or more manipulated digital signals triggers the measurement device.
19. The system of claim 1 , wherein:
the plurality of controlled circuits comprise a control device; and
one of the one or more manipulated digital signals triggers the operation of the control device.
20. The system of claim 1 , wherein:
the plurality of controlled circuits comprise an amplifier; and
one of the one or more manipulated digital signals controls a gain of the amplifier.