IMAGE SENSOR AND PIXEL ARRAY CIRCUIT THEREOF
An image sensor and a pixel array circuit thereof are provided. The image sensor includes the pixel array circuit and a readout circuit. The pixel array circuit includes pixel units. Each pixel unit includes a photo sensor, N storages, N transmission circuits, and M floating diffusion nodes. The N storages are coupled to the photo sensor and configured to store charges accumulated by the photo sensor at different exposures. Each transmission circuit is coupled between a corresponding storage and a corresponding floating diffusion node, and controlled by one of N transmission control signals to transmit the charges of the corresponding storage to the corresponding floating diffusion node during a certain time period. The readout circuit is coupled to the M floating diffusion nodes and configured to obtain N digital pixel values respectively corresponding to N image frames according to voltages of the M floating diffusion nodes of each pixel unit.
1 . An image sensor, comprising:
a pixel array circuit, comprising a plurality of pixel units, wherein each of the pixel units comprises:
M floating diffusion nodes;
a photo sensor, coupled to a first node;
N storages, coupled to the first node, and respectively configured to store charges accumulated by the photo sensor at different exposures, wherein N is a positive integer greater than or equal to two, and M is a positive integer less than or equal to N; and
N transmission circuits, wherein each of the N transmission circuits is coupled between one of the N storages and one of the M floating diffusion nodes, and is controlled by one of N transmission control signals to transmit the charges stored in the corresponding one of the N storages to the corresponding one of the M floating diffusion nodes during a specific time period; and
a readout circuit, coupled to the M floating diffusion nodes of each of the pixel units, and configured to obtain N digital pixel values respectively corresponding to N image frames according to voltages of the M floating diffusion nodes of each of the pixel units.
2 . The image sensor as claimed in claim 1 , wherein each of the N storages is an analog memory cell.
3 . The image sensor as claimed in claim 1 , wherein each of the N storages comprises:
a storage switch, having a first terminal coupled to the first node, a control terminal receiving one of N storage control signals, and a second terminal coupled to one of the N transmission circuits; and
a charge storage element, coupled to the second terminal of the storage switch, and configured to storage the charges from the photo sensor.
4 . The image sensor as claimed in claim 1 , wherein each of the N transmission circuits comprises:
a transmission switch, having a first terminal coupled to one of the N storages, a second terminal coupled to one of the M floating diffusion nodes, and a control terminal receiving one of the N transmission control signals; and
a reset switch, having a first terminal coupled to a reset power, a second terminal coupled to the corresponding one of the M floating diffusion nodes, and a control terminal receiving one of N reset control signals, wherein M is equal to N.
5 . The image sensor as claimed in claim 1 , wherein each of the N transmission circuits comprises:
a transmission switch, having a first terminal coupled to one of the N storages, a second terminal coupled to the M floating diffusion nodes, and a control terminal receiving one of the N transmission control signals,
wherein each of the pixel units further comprises:
a reset switch, having a first terminal coupled to a reset power, a second terminal coupled to the M floating diffusion nodes, and a control terminal receiving a reset control signal, wherein M is equal to one.
6 . The image sensor as claimed in claim 1 , wherein each of the pixel units further comprises:
a reset switch, having a first terminal coupled to a reset power, a second terminal coupled to the first node, and a control terminal receiving a reset control signal.
7 . The image sensor as claimed in claim 1 , wherein when the pixel array circuit performs an exposure operation, the photo sensors of the pixel units are simultaneously exposed.
8 . A pixel array circuit, comprising:
a plurality of pixel units, wherein each of the pixel units comprises:
M floating diffusion nodes;
a photo sensor, coupled to a first node;
N storages, coupled to the first node, and respectively configured to store charges accumulated by the photo sensor at different exposures, wherein N is a positive integer greater than or equal to two, and M is a positive integer less than or equal to N; and
N transmission circuits, wherein each of the N transmission circuits is coupled between one of the N storages and one of the M floating diffusion nodes, and is controlled by one of N transmission control signals to transmit the charges stored in the corresponding one of the N storages to the corresponding one of the M floating diffusion nodes during a specific time period.
9 . The pixel array circuit as claimed in claim 8 , wherein each of the N storages is an analog memory cell.
10 . The pixel array circuit as claimed in claim 8 , wherein each of the N storages comprises:
a storage switch, having a first terminal coupled to the first node, a control terminal receiving one of N storage control signals, and a second terminal coupled to one of the N transmission circuits; and
a charge storage element, coupled to the second terminal of the storage switch, and configured to storage the charges from the photo sensor.
11 . The pixel array circuit as claimed in claim 8 , wherein each of the N transmission circuits comprises:
a transmission switch, having a first terminal coupled to one of the N storages, a second terminal coupled to one of the M floating diffusion nodes, and a control terminal receiving one of the N transmission control signals; and
a reset switch, having a first terminal coupled to a reset power, a second terminal coupled to the corresponding one of the M floating diffusion nodes, and a control terminal receiving one of N reset control signals, wherein M is equal to N.
12 . The pixel array circuit as claimed in claim 8 , wherein each of the N transmission circuits comprises:
a transmission switch, having a first terminal coupled to one of the N storages, a second terminal coupled to the M floating diffusion nodes, and a control terminal receiving one of the N transmission control signals,
wherein each of the pixel units further comprises:
a reset switch, having a first terminal coupled to a reset power, a second terminal coupled to the M floating diffusion nodes, and a control terminal receiving a reset control signal, wherein M is equal to one.
13 . The pixel array circuit as claimed in claim 8 , wherein each of the pixel units further comprises:
a reset switch, having a first terminal coupled to a reset power, a second terminal coupled to the first node, and a control terminal receiving a reset control signal.
14 . The pixel array circuit as claimed in claim 8 , wherein when the pixel array circuit performs an exposure operation, the photo sensors of the pixel units are simultaneously exposed.