IP Library Granted Patent US 10,446,667
Granted Patent B2
US 10,446,667 · App. 16/404,749 · Granted Oct 15, 2019

Method for fabricating semiconductor device

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Quick Facts
Patent No.
US 10,446,667
App. No.
16/404,749
Granted
Oct 15, 2019
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.

Claims (16)

1. A method for fabricating semiconductor device, comprising:

forming a first gate structure on a substrate;

performing a first etching process to form a recess adjacent to the first gate structure;

performing an ion implantation process to form an amorphous layer directly under the recess;

performing a second etching process to remove the amorphous layer; and

forming an epitaxial layer in the recess.

2. The method of claim 1 , wherein the first etching process comprises a dry etching process.

3. The method of claim 1 , wherein ions implanted by the ion implantation process are selected from the group consisting of As, Ge, and P.

4. The method of claim 1 , wherein the second etching process comprises a wet etching process.

5. The method of claim 4 , wherein an etchant of the second etching process comprises NH 4 OH.

6. The method of claim 1 , further comprising performing the second etching process to remove the amorphous layer and at the same time forming a bump on the substrate directly under the recess.

7. The method of claim 6 , wherein a top surface of the bump comprises a planar surface.

8. The method of claim 6 , wherein the bump comprises two inclined sidewalls.

9. The method of claim 8 , further comprising forming the first gate structure and a second gate structure on the substrate, wherein the bump is between the first gate structure and the second gate structure.

10. The method of claim 9 , wherein the epitaxial layer comprises a first V-shape under the first gate structure and a second V-shape under the second gate structure.

11. The method of claim 10 , wherein the first V-shape and the second V-shape are connected to the two inclined sidewalls directly.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →