Lateral electrochemical cell with symmetric response for neuromorphic computing
A method of forming a resistive processing unit is provided. The method includes forming a spacer on a substrate. The method further includes forming an intercalation layer segment on opposite sides of the spacer, and replacing a portion of each of the intercalation layer segments with an insulating region. The method further includes replacing the spacer with an electrolyte layer.
1. A method of forming a resistive processing unit, comprising:
forming a spacer on a substrate;
forming an intercalation layer segment on opposite sides of the spacer;
replacing a portion of each of the intercalation layer segments with an insulating region; and
replacing the spacer with an electrolyte layer.
2. The method of claim 1 , further comprising forming an upper insulating layer on the electrolyte layer and intercalation layer segments.
3. The method of claim 2 , further comprising forming an upper trench to each of the intercalation layer segments in the upper insulating layer, and forming a conductive fill in each of the upper trenches.
4. The method of claim 1 , further comprising removing the insulating regions to form gaps adjoining each of the intercalation layer segments.
5. The method of claim 4 , further comprising forming a conducting junction layer in the gaps and on the intercalation layer segments.
6. The method of claim 5 , further comprising forming an interlayer dielectric (ILD) layer on the conducting junction layer, intercalation layer segments, and electrolyte layer.
7. The method of claim 1 , wherein the intercalation layer segments include a metal oxide material that undergoes a change in resistivity based on an amount of an intercalant.
8. The method of claim 7 , wherein the electrolyte layer is a solid electrolyte selected from the group consisting of LiPON, LiZrPO, Li 2 S, and sulfonated tetrafluoroethylene based fluoropolymer-copolymers.
9. The method of claim 8 , wherein the intercalant is selected from the group consisting of hydrogen (H), lithium (Li), sodium (Na), calcium (Ca), and combinations thereof.
10. A method of forming a resistive processing unit, comprising:
forming a plurality of lower conductive lines on an insulating region;
forming a lower insulating layer over the plurality of lower conductive lines;
forming a via to each of the plurality of lower conductive lines;
forming a plurality of spacers on the lower insulating layer, wherein each of the plurality of spacers is offset from one of the vias;
forming intercalation layer segments on the insulating layer; wherein the intercalation layer segments are on opposite sides of each of the plurality of spacers;
replacing a portion of each intercalation layer segments with an insulating region; and
replacing each of the plurality of spacers with an electrolyte layer.
11. The method of claim 10 , further comprising heat treating the intercalation layer segments at a temperature in a range of about 200° C. to about 700° C.
12. The method of claim 11 , wherein the intercalation layer segments include a metal oxide material that undergoes a change in resistivity based on an amount of an intercalant.
13. The method of claim 11 , further comprising forming an upper insulating layer on the electrolyte layer and intercalation layer segments.
14. The method of claim 13 , further comprising forming an upper trench to each of the intercalation layer segments in the upper insulating layer, and forming a conductive fill in each of the upper trenches, wherein each of the conductive fill in each of the upper trenches is in electrical contact with the same intercalation layer segment as the via.