Asymmetric gate edge spacing for SRAM structures
An integrated circuit having logic and static random-access memory (SRAM) devices includes at least three active regions with gate terminals. Dielectric pillars are disposed between the active regions of the integrated circuit. A pillar is disposed symmetrically between two active regions of the logic device. A pillar is disposed asymmetrically between a p-channel field effect transistor (pFET), and an n-channel field effect transistor (nFET) of the SRAM device.
1. A semiconductor device comprising:
at least three active regions comprising gate terminals; and
dielectric pillars disposed between active regions of the integrated circuit;
wherein an SRAM device pillar is disposed asymmetrically between a p-channel field effect transistor (pFET), and an n-channel field effect transistor (nFET); and
wherein a logic device pillar is disposed symmetrically between two active regions.
2. The semiconductor device according to claim 1 , wherein the SRAM device pillar is disposed closer to the pFET than the nFET.
3. The semiconductor device according to claim 1 , further comprising a dielectric gate cut disposed above a pillar.
4. The semiconductor device according to claim 1 , further comprising gate metal disposed above a pillar.
5. The semiconductor device according to claim 1 , wherein a top surface of a pillar is disposed higher than a top surface of a fin.
6. The semiconductor device according to claim 1 , wherein a top surface of a pillar is disposed below a top surface of a gate terminal.
7. The semiconductor device according to claim 1 , wherein the SRAM device pillar is disposed closer to the pFET than the nFET, further comprising:
a dielectric gate cut disposed above a first pillar; and
gate metal disposed above a second pillar.
8. A semiconductor device having SRAM devices, the semiconductor device comprising:
at least three active regions; and
a dielectric pillar disposed between two active regions;
wherein an SRAM device pillar is disposed asymmetrically between a p-channel field effect transistor (pFET), and an n-channel field effect transistor (nFET); and
wherein a logic device pillar is disposed symmetrically between two active regions.
9. The semiconductor device according to claim 8 , wherein the SRAM device pillar is disposed closer to the pFET than the nFET.
10. The semiconductor device according to claim 8 , further comprising a dielectric gate cut disposed above a pillar.
11. The semiconductor device according to claim 8 , wherein a top surface of a pillar is disposed higher than a top surface of a fin.
12. The semiconductor device according to claim 8 , wherein the SRAM device pillar is disposed closer to the pFET than the nFET, further comprising:
a dielectric gate cut disposed above the SRAM device pillar.