Transistors with electrically active chip seal ring and methods of manufacture
A transistor and method of manufacturing an electrically active chip seal ring surrounding the gate, gate insulator and source structure of the active core area of the transistor. The chip seal ring can be electrically coupled to the gate to seal the active core area from intrusions of contaminants, impurities, defects and or the like.
1. A transistor comprising:
a drain region disposed in a substrate;
a drift region disposed on the drain region;
one or more gate regions disposed in a core area of the substrate, and disposed down into the drift region;
one or more source regions disposed proximate the one or more gate regions;
one or more body regions disposed between the one or more source regions and the drift region, and disposed proximate the one or more gate regions;
one or more gate insulator regions disposed between the one or more gate regions and the one or more source regions, between the one or more gate regions and the one or more body regions, between the one or more gate regions and the drift region, and between the one or more gate regions and the drain region;
an electrically active chip seal ring region disposed down into the drift region in a periphery region surrounding the core area;
one or more dielectric layers disposed over the one or more gate regions, the one or more source regions, the one or more body regions, the one or more gate insulator regions and the electrically active ship seal ring region;
a metilization layer disposed over the one or more dielectric layers;
a chip seal ring contact extending through the one or more dielectric layers between the metallization layer to the electrically active ship seal ring region, and extending around the electrically active chip seal ring region; and
one or more gate contacts extending through the one or more dielectric layers between the metalization layer and the one or more gate regions.
2. The transistor of claim 1 , wherein:
the drain region comprises a heavily n-doped semiconductor;
the drift region comprises a moderate or lightly n-doped semiconductor;
the one or more body regions comprise a moderately p-doped semiconductor;
the one or more source regions comprise a heavily n-doped semiconductor; and
the electrically active chip seal ring region comprises a heavily n-doped semiconductor.
3. The transistor of claim 1 , wherein electrically active chip seal ring region, the metalization layer and the chip seal ring extending around the electrically active chip seal ring region enclose the one or more gate regions and one or more source regions.
4. The transistor of claim 1 , further comprising a chip seal ring insulator region disposed between the electrically active chip seal ring region and the one or more body regions.
5. The transistor of claim 4 , further comprising a first electrically active chip seal ring region disposed between a second electrically active chip seal ring region and the drain region, wherein the chip seal ring insulator region is further disposed between the first and second electrically active chip seal ring regions and the one or more body regions.
6. The transistor of claim 4 , wherein the body region extends continuously between the chip seal ring insulator region and the one or more gate insulator regions.
7. A transistor comprising:
a drain region;
a drift region disposed on the drain region;
one or more gate regions disposed down into the drift region;
one or more source regions;
one or more body regions disposed between the one or more source regions and the drift region, and disposed proximate the one or more gate regions;
one or more gate insulator regions disposed between the one or more gate regions and the one or more source regions, between the one or more gate regions and the one or more body regions, between the one or more gate regions and the drift region, and between the one or more gate regions and the drain region;
an electrically active chip seal ring region disposed down into the drift region and surrounding the structure of the one or more gate region, one or more gate insulator regions and the one or more source regions,
a chip seal ring insulator region disposed between the electrically active chip seal ring region and the body region and between the electrically active chip seal ring and the drift region;
first metalization layer disposed over the one or more gate regions, the one or more source region, the one or more body regions, the one or more gate insulator regions and the electrically active chip seal ring region;
a chip seal ring contact extending around the electrically active chip seal ring region, and coupled between the first metalization layer and the electrically active chip seal ring region;
one or more gate contact coupled between the first metilization layer and the one or more gate regions; and
one or more dielectric layers disposed between the first metalization layer and the one or more source regions, between the first metalization layer and the one or more body regions, and between the first metalization layer and the one or more gate regions.
8. The transistor of claim 7 , wherein the chip seal ring contact, the first metalization layer and the electrically active chip seal ring region are configured to seal the structure of the one or more gate regions, one or more gate insulator regions and the one or more source regions from contaminants migrating in through the one or more dielectric layers.
9. The transistor of claim 7 , wherein:
the drain region comprises a heavily n-doped semiconductor;
the drift region comprises a moderate or lightly n-doped semiconductor;
the one or more body regions comprise a moderately p-doped semiconductor;
the one or more source regions comprise a heavily n-doped semiconductor;
the one or more gate insulator regions comprise an oxide or dielectric; and
the electrically active chip seal tin region comprises a heavily n-doped semiconductor.
10. The transistor of claim 7 , wherein the one or more body regions extend continuously between the one or more gate insulator regions and the chip seal ring insulator region.