Light emitting diode chip and fabrication method

1. A fabrication method of a light-emitting diode chip, comprising:

1) providing a light-emitting epitaxial laminated layer including a first-type semiconductor layer, a second-type semiconductor layer, and an active layer therebetween, wherein the light-emitting epitaxial laminated layer has a first surface and an opposing second surface, and wherein the second surface is a light-emitting surface;

2) fabricating a first electrical connection layer over the first surface of the light-emitting epitaxial laminated layer and having first geometric pattern arrays; and

forming a first dielectric material over the first electrical connection layer;

3) fabricating a second electrical connection layer over the second surface of the light-emitting epitaxial laminated layer and having second geometric pattern arrays;

4) fabricating a transparent current spreading layer over the surface of the second electrical connection layer; wherein when external power is connected, a horizontal resistance of a current passing through the transparent current spreading layer is less than a current passing through the second electrical connection layer;

wherein step 3) comprises evaporating a second electrical connection layer over the second surface of the light-emitting epitaxial laminated layer; evaporating a second dielectric material over a surface of the second electrical connection layer;

etching a region of the second dielectric material to expose the second electrical connection layer; and flattening the surface of the second connection layer through chemical mechanical polishing.

2. The fabrication method of claim 1 , further comprising step 5): fabricating a first electrode over the transparent current spreading layer, in which, when current is injected to the first electrode and conducted to the transparent current spreading layer, it is horizontally conducted in priority before injection to the first electrical connection layer.

3. A light-emitting diode chip, comprising:

a light-emitting epitaxial laminated layer including a first-type semiconductor layer, a second-type semiconductor layer, and an active layer therebetween, wherein the light-emitting epitaxial laminated layer has a first surface and an opposing second surface, and wherein the second surface is a light-emitting surface;

a first electrical connection layer over the first surface of the light-emitting epitaxial laminated layer and having first geometric pattern arrays;

a first dielectric material over the first electrical connection layer;

a second electrical connection layer evaporated over the second surface of the light-emitting epitaxial laminated layer and having second geometric pattern arrays;

a second dielectric material over a surface of the second electrical connection layer having a region etched to expose the second electrical connection layer, wherein the surface of the second electrical connection layer is flattened through chemical mechanical polishing; and

a transparent current spreading layer over a surface of the second electrical connection layer;

wherein, when external power is connected, a horizontal resistance of a current passing through the transparent current spreading layer is less than a current passing through the second electrical connection layer.

4. The light-emitting diode chip of claim 3 , wherein the light-emitting epitaxial laminated layer comprises an AlGaInP-based material.

5. The light-emitting diode chip of claim 3 , further comprising a top electrode over the second electrical connection layer, wherein when a current is injected to the top electrode and conducted to the transparent current spreading layer, the current is horizontally conducted in priority prior to injection to the second electrical connection layer.

6. The light-emitting diode chip of claim 5 , wherein the first geometric pattern array and the second geometric pattern array are alternatively arranged.

7. The light-emitting diode chip of claim 5 , wherein an average surface roughness of the second electrical connection layer Ra is 1 nm or lower.

8. The light-emitting diode chip of claim 5 , wherein the second electrical connection layer is AuGe, AuGeNi, or TiAu alloy.

9. The light-emitting diode chip of claim 5 , wherein the first geometric pattern array is not connected due to isolation by the first dielectric material, and the second geometric pattern array is not connected due to isolation by the second dielectric material.

10. The light-emitting diode chip of claim 9 , wherein the second dielectric material is composed of anti-reflection single-layer or multi-layer materials, and is configured to increase light source radiation penetration of the active layer and reduce optical loss.

11. The light-emitting diode chip of claim 9 , wherein the first dielectric material is composed of single-layer or multi-layer materials, which reflects radiation light source of the active layer and reduces optical loss.

12. The light-emitting diode chip of claim 9 , wherein the second geometric pattern array area equals to or is less than 1/10 of the light-emitting area of the light-emitting epitaxial laminated layer.

13. A light-emitting system comprising a plurality of light-emitting diodes, each light-emitting diode including:

a light-emitting epitaxial laminated layer including a first-type semiconductor layer, a second-type semiconductor layer, and an active layer therebetween, wherein the light-emitting epitaxial laminated layer has a first surface and an opposing second surface, and wherein the second surface is a light-emitting surface;

a first electrical connection layer over the first surface of the light-emitting epitaxial laminated layer and having first geometric pattern arrays;

a first dielectric material over the first electrical connection layer;

a second electrical connection layer evaporated over the second surface of the light-emitting epitaxial laminated layer and having second geometric pattern arrays;

a second dielectric material over a surface of the second electrical connection layer having a region etched to expose the second electrical connection layer, wherein the surface of the second electrical connection layer is flattened through chemical mechanical polishing; and

a transparent current spreading layer over a surface of the second electrical connection layer;

wherein, when external power is connected, a horizontal resistance of a current passing through the transparent current spreading layer is less than a current passing through the second electrical connection layer.

14. The light-emitting system of claim 13 , wherein each light-emitting diode further comprises a top electrode over the second electrical connection layer, wherein when current is injected to the top electrode and conducted to the transparent current spreading layer, the current is horizontally conducted in priority prior to injection to the second electrical connection layer.

15. The light-emitting system of claim 14 , wherein the first geometric pattern array and the second geometric pattern array are alternatively arranged.

16. The light-emitting system of claim 14 , wherein an average surface roughness of the second electrical connection layer Ra is 1 nm or lower.

17. The light-emitting system of claim 14 , wherein the first geometric pattern array is not connected due to isolation by the first dielectric material, and the second geometric pattern array is not connected due to isolation by the second dielectric material.

18. The light-emitting diode system of claim 17 , wherein the first dielectric material is composed of single-layer or multi-layer materials, and is configured to reflect radiation of the active layer and reduce optical loss.

19. The light-emitting diode system of claim 17 , wherein the second geometric pattern array area equals to or is less than 1/10 of the light-emitting area of the light-emitting epitaxial laminated layer.