3D semiconductor device and structure

1. A 3D semiconductor device, the device comprising:

a first level comprising a first single crystal layer;

first transistors overlaying said first single crystal layer;

second transistors overlaying said first transistors; and

a second level comprising a second single crystal layer, said second level overlays said second transistors,

wherein said first transistors and said second transistors each comprises a polysilicon channel.

2. The device according to claim 1 ,

wherein said first transistors and said second transistors are junction-less transistors,

wherein each of said junction-less transistors comprises a source, a channel, and a drain, and

wherein said source, said channel, and said drain comprise a similar doping type.

3. The device according to claim 1 ,

wherein said first level comprises a via through said first single crystal layer.

4. The device according to claim 1 ,

wherein said second level comprises a via through said second single crystal layer.

5. The device according to claim 1 ,

wherein said first transistors and said second transistors are self-aligned, being processed following the same lithography step.

6. The device according to claim 1 ,

wherein said device comprises an array of memory cells,

wherein a plurality of said memory cells comprises at least one of said second transistors, and

wherein said second level comprises a periphery circuit to control said array of memory cells.

7. The device according to claim 1 ,

wherein said second single crystal layer comprises third transistors, and

wherein said third transistors are aligned to said first transistors with less than 150 nm misalignment.

8. A 3D semiconductor device, the device comprising:

a first level comprising a first single crystal layer;

first transistors overlaying said first single crystal layer;

second transistors overlaying said first transistors; and

a second level comprising a second single crystal layer, said second level overlaying said second transistors,

wherein said first transistors and said second transistors are junction-less transistors.

9. The device according to claim 8 ,

wherein said junction-less transistors each comprise a source, a channel, and a drain, and

wherein said source, said channel, and said drain have a similar doping type.

10. The device according to claim 8 ,

wherein said second transistors each comprise a polysilicon channel.

11. The device according to claim 8 ,

wherein said first level comprises a via through said first single crystal layer.

12. The device according to claim 8 ,

wherein said second level comprises a via through said second single crystal layer.

13. The device according to claim 8 ,

wherein said first transistors and said second transistors are self-aligned, being processed following the same lithography step.

14. The device according to claim 8 ,

wherein said device comprises an array of memory cells,

wherein a plurality of said memory cells comprise at least one of said second transistors, and

wherein said second level comprises a periphery circuit to control said array of memory cells.

15. A 3D semiconductor device, the device comprising:

a first level comprising a first single crystal layer;

first transistors overlaying said first single crystal layer;

second transistors overlaying said first transistors;

third transistors overlaying said second transistors;

fourth transistors overlaying said third transistors;

a second level comprising a second single crystal layer, said second single crystal layer overlaying said fourth transistor,

wherein said second transistors, said third transistors, and said fourth transistors are self-aligned, being processed following the same lithography step; and

a memory peripheral circuit,

wherein said memory peripheral circuit comprises at least one of said first transistors, and

wherein said memory peripheral circuit controls at least one of said second transistors, at least one of said third transistors, and at least one of said fourth transistors.

16. The device according to claim 15 ,

wherein at least one of said third transistors comprises a source, channel, and drain, and

wherein said source, said channel, and said drain have a similar doping type.

17. The device according to claim 15 ,

wherein said third transistors each comprise a polysilicon channel.

18. The device according to claim 15 ,

wherein said first level comprises connections to an external device, and

wherein said connection comprises a via through said first single crystal layer.

19. The device according to claim 15 ,

wherein said second level comprises fifth transistors,

wherein said fifth transistors each comprise a transistor channel, and

wherein said transistor channel comprises said second single crystal.

20. The device according to claim 15 , further comprising:

a memory cell,

wherein said memory cell comprises at least one of said third transistors.