Overshoot current detection and correction circuit for electrical fast transient events
A positive overshoot detection circuit comprises a transistor coupled to a current mirror, a reference current source coupled to the current mirror, and a comparator coupled to the reference current source and the current mirror. The comparator output indicates whether the current mirror's current is greater than the reference current source's current. A control input and a current terminal of the transistor are coupled to a clamping circuit. A negative overshoot detection circuit comprises a biasing sub-circuit coupled to a transistor, a resistor coupled to the transistor, and a comparator coupled to the transistor and the resistor. The comparator output indicates whether the transistor is in an on or off state. The biasing sub-circuit is coupled to a clamping circuit. In some implementations, the comparator outputs from the positive and negative overshoot detection circuits are provided to a driver circuit, which modifies its operation.
1. A clamping and detection circuit, comprising:
a clamping sub-circuit, comprising:
a first clamping transistor coupled to a bus node and a first node,
a first diode coupled to the bus node and the first node,
a first high pass filter coupled to the bus node and a control input of the first clamping transistor,
a second clamping transistor coupled to the first node and a common mode node,
a second diode coupled to the first node and the common mode node, and
a second high pass filter coupled to the common mode node and a control input of the second clamping transistor;
a positive overshoot current detection sub-circuit, comprising:
a first transistor coupled to the first node,
a current mirror coupled to the first transistor,
a reference current source coupled to the current mirror at a second node, and
a first comparison device coupled to the second node; and
a negative overshoot current detection sub-circuit, comprising:
a biasing sub-circuit coupled to the first node,
a second transistor coupled to the biasing sub-circuit,
a resistor coupled to a supply voltage node and the second transistor at a third node, and
a second comparison device coupled to the third node.
2. The clamping and detection circuit of claim 1 , wherein the resistor is a first resistor and wherein the biasing sub-circuit comprises:
a third diode coupled to the first node and the control input of the second transistor;
a second resistor coupled to the supply voltage node and the control input of the second transistor; and
a third resistor coupled to the control input of the second transistor and the common mode node.
3. The clamping and detection circuit of claim 1 , wherein the first clamping transistor, the second clamping transistor, and the first transistor are p-type metal oxide semiconductor field effect transistors.
4. The clamping and detection circuit of claim 1 , wherein the second transistor is an n-type metal oxide semiconductor field effect transistor.
5. The clamping and detection circuit of claim 1 , wherein the control input of the first transistor is coupled to the control input of the second clamping transistor.
6. The clamping and detection circuit of claim 1 , wherein an output of the first comparison device is indicative of whether a current output by the current mirror is greater than a current generated by the reference current source.
7. The clamping and detection circuit of claim 1 , wherein an output of the second comparison device is indicative of whether the second transistor is in an off state.
8. The clamping and detection circuit of claim 1 , wherein an output of the first comparison device and an output of the second comparison device are provided to a driver circuit.
9. The clamping and detection circuit of claim 8 , wherein the outputs of the first and the second comparison devices cause modifications to operation of the driver circuit.
10. A circuit comprising:
a silicon controlled rectifier (SCR) circuit;
a clamping sub-circuit comprising:
a first transistor having a first current terminal, a second current terminal, and a first control terminal, the first current terminal coupled to the SCR circuit;
a first high pass filter coupled to the first control terminal and the first current terminal;
a second transistor having a third current terminal, a fourth current terminal, and a second control terminal, the third current terminal coupled to the second current terminal and the fourth current terminal coupled to the SCR circuit; and
a second high pass filter coupled to the second control terminal and to the fourth current terminal; and
a negative overshoot current detection sub-circuit comprising:
a biasing sub-circuit coupled to the second current terminal;
a third transistor having a fifth current terminal, a sixth current terminal, and a third control terminal, the third control terminal coupled to the biasing sub-circuit and the sixth current terminal coupled to the fourth current terminal;
a resistor coupled to the fifth current terminal and to the biasing circuit; and
a comparison device coupled to the fifth current terminal.
11. The circuit of claim 10 , the clamping sub-circuit further comprising:
a first diode coupled to the first current terminal and to the second current terminal; and
a second diode coupled to the third current terminal and to the fourth current terminal.
12. The circuit of claim 10 , wherein the resistor is a first resistor and the biasing sub-circuit comprises:
a second resistor coupled to the first resistor and to the third control terminal;
a third resistor coupled to the third control terminal and to the sixth current terminal; and
a diode coupled between the third control terminal and the second current terminal.
13. The circuit of claim 10 , wherein the comparison device is configured to output a signal indicative of an on state or an off state of the third transistor.
14. The circuit of claim 10 , wherein an output of the comparison device is adapted to be coupled to a driver circuit.
15. The circuit of claim 10 , wherein the comparison device is a first comparison device, the circuit further comprising a positive overshoot current detection sub-circuit comprising:
a fourth transistor coupled to the first transistor and to the second transistor;
a current mirror coupled to the fourth transistor; and
a second comparison device coupled to the current mirror.
16. The circuit of claim 15 , further comprising a current source coupled to the current mirror and to the second comparison device.