Method and apparatus to perform dynamic frequency scaling while a phase-locked loop operates in a closed loop
Dynamic voltage frequency scaling to transition to a target clock frequency and associated target voltage is provided. Dynamic voltage frequency scaling to a different clock frequency is performed by gradually changing the clock frequency using discrete variable-size steps, while dynamically switching to faster or slower reference clock frequencies as appropriate to harmonize the frequency trajectory with system requirements.
1. An apparatus comprising:
a phase-locked loop to generate an output clock having a frequency dependent on a reference clock and a feedback clock; and
frequency crawl circuitry communicatively coupled to the phase-locked loop, to dynamically select the reference clock and the feedback clock to adjust the frequency in discrete variable-size frequency steps until the frequency is at a target frequency, a size of a frequency step is a smallest frequency step or a multiple of the smallest frequency step, the phase-locked loop operates in closed loop while the frequency is adjusted.
2. The apparatus of claim 1 , wherein the frequency is increased while an associated voltage is gradually ramped up to a target voltage.
3. The apparatus of claim 1 , wherein the frequency is decreased while an associated voltage is gradually ramped down to a target voltage.
4. The apparatus of claim 1 , wherein the phase-locked loop is analog.
5. The apparatus of claim 1 , wherein the phase-locked loop is digital.
6. The apparatus of claim 1 , wherein the size of the frequency step is dependent on a nearest faster reference clock.
7. The apparatus of claim 1 , wherein the size of the frequency step is selected to not overshoot the target frequency.
8. The apparatus of claim 1 , wherein the size of the frequency step is selected to not undershoot the target frequency.
9. A method comprising:
generating, by a phase-locked loop, an output clock having a frequency dependent on a reference clock and a feedback clock; and
dynamically selecting the reference clock and the feedback clock to adjust the frequency in discrete variable-size frequency steps until the frequency is at a target frequency, a size of a frequency step is a smallest frequency step or a multiple of the smallest frequency step, the phase-locked loop operates in closed loop while the frequency is adjusted.
10. The method of claim 9 , wherein the frequency is increased while an associated voltage is gradually ramped up to a target voltage.
11. The method of claim 9 , wherein the frequency is decreased while an associated voltage is gradually ramped down to a target voltage.
12. The method of claim 9 , wherein the phase-locked loop is analog.
13. The method of claim 9 , wherein the phase-locked loop is digital.
14. The method of claim 9 , wherein the size of the frequency step is dependent on a nearest faster reference clock.
15. The method of claim 9 , wherein the size of the frequency step is selected to not overshoot the target frequency.
16. The method of claim 9 , wherein the size of the frequency step is selected to not undershoot the target frequency.
17. A system comprising:
a processor, the processor comprising:
a phase-locked loop to generate an output clock having a frequency dependent on a reference clock and a feedback clock; and
frequency crawl circuitry communicatively coupled to the phase-locked loop, to dynamically select the reference clock and the feedback clock to adjust the frequency in discrete variable-size frequency steps until the frequency is at a target frequency, a size of a frequency step is a smallest frequency step or a multiple of the smallest frequency step, the phase-locked loop operates in closed loop while the frequency is adjusted; and
a display communicatively coupled to the processor.
18. The apparatus of claim 1 , wherein the smallest frequency step is equal or less than 16.67 Mega Hertz.
19. The method of claim 9 , wherein the smallest frequency step is equal or less than 16.67 Mega Hertz.
20. The system of claim 17 , wherein the smallest frequency step is equal or less than 16.67 Mega Hertz.