Compact diode laser source
A compact diode laser achieves high-power, short duration output pulses by separating the lasing action from the pulse-generating mechanism. A diode seed source is configured for gain-switching via a variable RF source. A time lens element includes an intensity modulation device, a phase modulation device, and a pulse compressor. The intensity modulation device carves shorter pulses from the long gain-switched seed pulses, the phase modulation device adds chirp, and the pulse compressor compensates for the chirp while producing high-power short-duration output pulses.
1. A pulsed laser comprising:
a semiconductor seed pulse source configured for generating seed pulses via gain-switching;
a time lens element including a phase modulation device, a pulse compressor, and an intensity modulation device configured to carve shorter pulses from the seed pulses; and
a clock signal source;
wherein a seed pulse repetition rate is based upon the clock signal;
wherein the phase modulation device adds chirp to the seed pulses; and
wherein the pulse compression device is configured to compensate for the chirp and produce high peak power, short-duration output pulses.
2. The pulsed laser of claim 1 wherein the duration of the output pulses is less than 1/10 of the duration of the seed pulses.
3. The pulsed laser of claim 1 wherein the time lens element includes only a single intensity modulation device and only a single phase modulation device.
4. The pulsed laser of claim 1 further comprising a modulation driver configured to temporally align the intensity modulation device and the phase modulation device.
5. The pulsed laser of claim 1 configured without free-space elements.
6. The pulsed laser of claim 1 configured to generate output pulses exceeding 100 pJ.
7. The pulsed laser of claim 1 configured to generate output pulses in the region of 900-1000 nm.
8. The pulsed laser of claim 1 configured to generate output pulses below about 5 ps.
9. The pulsed laser of claim 1 wherein the phase modulation device is configured to provide programmable chirp according to a variable drive voltage.
10. A pulsed laser comprising:
a semiconductor seed pulse source configured for generating seed pulses via gain-switching;
a time lens element including a phase modulation device and a pulse compressor; and
a clock signal source comprising an RF synthesizer and a variable frequency divider;
wherein a seed pulse repetition rate is based upon the clock signal;
wherein the phase modulation device adds chirp to the seed pulses; and
wherein the pulse compression device is configured to compensate for the chirp and produce high peak power, short-duration output pulses.
11. The pulsed laser of claim 10 wherein the variable frequency divider comprises a variable divide-by-N counter.
12. The pulsed laser of claim 11 wherein the clock signal source produces clock signals within the range of 67 kHz to 10 MHz.
13. The pulsed laser of claim 10 wherein the variable frequency divider comprises a phase-locked loop.
14. The pulsed laser of claim 10 configured without free-space elements.
15. The pulsed laser of claim 10 wherein the pulse compressor comprises one of the following:
diffraction gratings;
a fiber Bragg grating;
a volume Bragg grating;
a length of dispersive optical fiber;
prisms; or
grisms.
16. The pulsed laser of claim 1 configured to generate output pulses exceeding 100 pJ.
17. The pulsed laser of claim 1 configured to generate output pulses in the region of 900-1000 nm.
18. The pulsed laser of claim 1 configured to generate output pulses below about 5 ps.
19. The method of generating pulses comprising the steps of:
(a) generating seed pulses with a gain-switched semiconductor laser;
(b) generating a clock signal with an RF synthesizer and a variable frequency divider and basing a seed pulse repetition rate upon the clock signal;
(c) applying chirp to the seed pulses;
(d) compressing the chirped pulses to compensate for the chirp and produce high-power short-duration output pulses.
20. The method of claim 19 wherein the variable frequency divider comprises a divide-by-N counter.
21. The method of claim 19 wherein the variable frequency divider comprises a phase-locked loop.