Cross-polarized time division duplexed antenna

1. A laminar phased array antenna comprising:

a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, the first polarity being physically orthogonal to the second polarity;

a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity; and

a controller configured to control the first sub-array and the second sub-array to operate together in either a receive mode or in a transmit mode,

wherein each of the first sub-array and the second sub-array includes a laminar substrate, a plurality of elements configured to form a patch-based phased array, and a plurality of integrated circuits configured to control one or more of receipt and transmission of signals by the plurality of elements,

and wherein each of the plurality of elements is physically coupled with a first integrated circuit interface at a first location on the element and a second integrated circuit interface at a second location on the element, the signals interfacing with the first integrated circuit interface being in the first polarity, the signals interfacing with the second integrated circuit interface being in the second polarity, the first and second locations being spaced apart.

2. The laminar phased array antenna of claim 1 , wherein:

the first sub-array and the second sub-array being configured to operate at the same time to receive signals in the first polarity and the second polarity when in the receive mode, and

the first sub-array and the second sub-array being configured to operate at the same time to transmit signals in the first polarity and the second polarity when in the transmit mode.

3. The laminar phased array antenna of claim 1 , wherein the plurality of integrated circuits include one or more receive-only integrated circuits and one or more transmit-only integrated circuits.

4. The laminar phased array antenna of claim 1 , wherein the plurality of integrated circuits include one or more dual transmit/receive integrated circuits.

5. The laminar phased array antenna of claim 1 , wherein the plurality of integrated circuits are configured to operate the phased array to communicate signals using 5G protocols.

6. The laminar phased array antenna of claim 1 , wherein the first polarity includes a vertical polarity and the second polarity includes a horizontal polarity.

7. The laminar phased array antenna of claim 1 , wherein the first polarity includes a horizontal polarity and the second polarity includes a vertical polarity.

8. The laminar phased array antenna of claim 1 , wherein each of the first sub-array and the second sub-array is transmit/receive switch-free.

9. The laminar phased array antenna of claim 1 , wherein the first sub-array includes a first laminar substrate, and the second sub-array includes a second laminar substrate, the first laminar substrate and the second laminar substrate being the respective laminar substrates of the first and second sub-arrays and being different substrates.

10. The laminar phased array antenna of claim 1 , wherein the respective laminar substrates of the first sub-array and the second sub-array are configured on a single laminar substrate.

11. A beam forming integrated circuit, comprising:

a plurality of integrated circuit interfaces, each of the plurality of integrated circuit interfaces being configured to communicate signals in one of a first polarity and a second polarity to or from a respective location at a corresponding antenna element;

wherein the beam forming integrated circuit is disposed within one of a first sub-array and a second sub-array included in a phased array antenna,

the first sub-array being configured to operate in one of a receive mode with the first polarity and a transmit mode with the second polarity, the first polarity being physically orthogonal to the second polarity, and

the second sub-array being configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity,

wherein each of the first sub-array and the second sub-array includes a laminar substrate, a plurality of elements configured to form a patch-based phased array,

and wherein each of the plurality of elements is physically coupled with a first integrated circuit interface at a first location on the element and a second integrated circuit interface at a second location on the element, the signals interfacing with the first integrated circuit interface being in the first polarity, the signals interfacing with the second integrated circuit interface being in the second polarity, the first and second locations being spaced apart.

12. The beam forming integrated circuit of claim 11 , wherein the first sub-array and the second sub-array are configured to operate together in the receive mode such that the first sub-array and the second sub-array receive incoming signals in the first polarity and incoming signals in the second polarity at the same time.

13. The beam forming integrated circuit of claim 11 , wherein the first sub-array and the second sub-array are configured to operate together in the transmit mode such that the first sub-array and the second sub-array transmit outgoing signals in the first polarity and output signals in the second polarity at the same time.

14. The beam forming integrated circuit of claim 11 , wherein the beam forming integrated circuit is a receive-only integrated circuit and the plurality of integrated circuit interfaces are configured to receive incoming signals in one of a horizontal polarity and a vertical polarity.

15. The beam forming integrated circuit of claim 11 , wherein the beam forming integrated circuit is a transmit-only integrated circuit and the plurality of integrated circuit interfaces are configured to transmit outgoing signals in one of a horizontal polarity and a vertical polarity.

16. The beam forming integrated circuit of claim 11 , wherein the beam forming integrated circuit is a dual transmit/receive integrated circuit and wherein one or more of the plurality of integrated circuit interfaces are configured to receive incoming signals in a horizontal polarity and one or more of the plurality of integrated interfaces are configured to transmit outgoing signals in a vertical polarity.

17. The beam forming integrated circuit of claim 11 , wherein the beam forming integrated circuit is a dual transmit/receive integrated circuit and wherein one or more of the plurality of integrated circuit interfaces are configured to receive incoming signals in a vertical polarity and one or more of the plurality of integrated interfaces are configured to transmit outgoing signals in a horizontal polarity.

18. A laminar phased array comprising:

a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, the first polarity being physically orthogonal to the second polarity;

a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity; and

means for controlling the first sub-array and the second sub-array to operate together in either a receive mode or in a transmit mode,

wherein each of the first sub-array and the second sub-array includes a laminar substrate, a plurality of elements configured to form a patch-based phased array, and a plurality of integrated circuits configured to control one or more of receipt and transmission of signals by the plurality of elements,

and wherein each of the plurality of elements is physically coupled with a first integrated circuit interface at a first location on the element and a second integrated circuit interface at a second location on the element, the signals interfacing with the first integrated circuit interface being in the first polarity, the signals interfacing with the second integrated circuit interface being in the second polarity, the first and second locations being spaced apart.

19. The laminar phased array of claim 18 , wherein the plurality of integrated circuits include one or more receive-only integrated circuits and one or more transmit-only integrated circuits.

20. The laminar phased array of claim 18 , wherein each of the first sub-array and the second sub-array is transmit/receive switch-free.