Phase accumulator with improved accuracy
A PLL includes a controlled oscillator, a phase accumulator to measure the controlled oscillator output phase, a phase predictor to calculate the required output phase, and a phase subtractor to calculate the phase difference or phase error. The phase accumulator includes a counter whose output sequence changes only one bit per counted controlled oscillator output cycle, such as a Gray counter. It further includes a register or latches, which sample(s) the counter output value upon receiving a reference clock pulse. The latches output value represents the measured phase. A binary encoder, such as a Gray-to-binary converter, may translate the measured phase to a binary number. The phase accumulator may further include a delay line, second latches, and a delay line decoder to measure a fractional part of the phase. A calibration feedback loop may keep the number of delay line steps per output clock pulse known and stable.
1. A phase-locked loop (PLL) including a phase accumulator, comprising:
a counter configured to count cycles of a controlled-oscillator clock signal, wherein a counter output sequence changes in only one bit per counted controlled-oscillator clock signal cycle; and
first latches coupled with a counter output and configured to sample and store a counter output value upon receiving a reference clock signal, the counter value representing an integer output phase.
2. The PLL of claim 1 , wherein the counter includes a modulo-K counter.
3. The PLL of claim 1 , wherein the counter is configured to output a sequence that includes a Gray code.
4. The PLL of claim 1 , further comprising a binary encoder to convert the integer output phase to a binary number.
5. The PLL of claim 4 , wherein the binary encoder includes a Gray-to-binary converter.
6. The PLL of claim 1 , further comprising:
a delay line configured to receive the controlled-oscillator clock signal and including multiple output taps along which the received controlled-oscillator clock signal propagates;
second latches coupled with the delay line output taps and configured to sample and store delay line output tap values upon receiving the reference clock signal; and
a delay line decoder coupled with outputs of the second latches and configured to translate a series of successive equal bit values signifying fractional progress of a controlled-oscillator clock signal pulse to a binary number representing a fractional output phase.
7. A method to measure a PLL's output clock phase, comprising the following steps:
(a) in a phase accumulator, receiving the PLL's output clock and counting output clock pulses in a counter whose output value changes only one bit per counted output clock pulse; and
(b) in a register, upon receiving a reference clock pulse, sampling and storing the counter output value.
8. The method of claim 7 , further comprising:
(c) converting the output value stored in the register to a binary number.