Method of forming FinFET structure with reduced Fin buckling

1. A method of forming an integrated circuit structure, the method comprising:

forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and

patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

2. The method of claim 1 , wherein

the first stress layer has a first density; and

the second stress layer has a second density less than the first density.

3. The method of claim 1 , wherein

the first stress layer has the first compressive stress less than 0.5 GPa; and

the second stress layer has the second compressive stress greater than 2.5 GPa.

4. The method of claim 3 , wherein

the first compressive stress of the first stress layer ranges between 0.2 GPa and 0.4 GPa; and

the second compressive stress of the second stress layer ranges between 2.8 GPa and 3.0 GPa.

5. The method of claim 4 , wherein

the forming of the first stress layer includes depositing a first silicon nitride layer by chemical vapor deposition (CVD) using a first precursor including dichlorosilane (SiH 2 Cl 2 ), NH 3 and H 2 ; and

the forming of the second stress layer includes depositing a second silicon nitride layer by CVD using a second precursor including dichlorosilane and NH 3 , the second precursor being free of H 2 .

6. The method of claim 1 , wherein

the first stress layer has a first Young's module; and

the second stress layer has a second Young's module less than the first Young's module.

7. The method of claim 1 , wherein the forming of the composite stress layer further includes forming a third stress layer disposed between the first and second stress layers, wherein the third stress layer has a tensile stress while the first and second stress layer have compressive stresses.

8. The method of claim 7 , wherein the forming of the third stress layer includes forming an amorphous silicon layer having the tensile stress ranging between −0.3 GPa and −0.5 GPa.

9. The method of claim 8 , wherein

the forming of the first stress layer includes forming the first stress layer by CVD with first deposition temperature;

the forming of the second stress layer includes forming the second stress layer by CVD with second deposition temperature; and

the forming of the third stress layer includes forming the amorphous silicon layer by CVD using a precursor having Si 2 H 6 with a third deposition temperature less than the first and second deposition temperatures.

10. The method of claim 1 , wherein the patterning of the semiconductor substrate to form the fin active regions further includes:

patterning the composite stress layer;

etching the semiconductor substrate to form trenches using the patterned composite stress layer as an etch mask;

filling the trenches with a dielectric material to form isolation features; and

recessing the isolation features so that the fin active regions are extruded above the recessed isolation features.

11. The method of claim 10 , further comprising forming gate stacks on the fin active regions, the gate stacks include a high-k dielectric material and metal.

12. A method of forming an integrated circuit structure, the method comprising:

forming a first stress layer of a first compressive stress on a semiconductor substrate;

forming a second stress layer of a second compressive stress over the first stress layer;

forming a third stress layer of a tensile stress between the first and second stress layers; and

patterning the semiconductor substrate to form fin active regions using the first, second and third stress layers as an etch mask.

13. The method of claim 12 , wherein

the forming of the first stress layer of the first compressive stress includes forming the first stress layer of silicon nitride;

the forming of the second stress layer of the second compressive stress includes forming the second stress layer of silicon nitride; and

the forming of the third stress layer of the tensile stress includes forming the third stress layer of amorphous silicon.

14. The method of claim 13 , wherein the second compressive stress is greater than the first compressive stress.

15. The method of claim 14 , wherein

the first compressive stress of the first stress layer is less than 0.5 GPa; and

the second compressive stress of the second stress layer is greater than 2.5 GPa.

16. The method of claim 12 , wherein

the first stress layer has a first density; and

the second stress layer has a second density less than the first density.

17. The method of claim 16 , wherein

the forming of the first stress layer includes depositing a first silicon nitride layer by chemical vapor deposition (CVD) using a first precursor including dichlorosilane (SiH 2 Cl 2 ), NH 3 and H 2 ; and

the forming of the second stress layer includes depositing of a second silicon nitride layer by CVD using a second precursor including dichlorosilane and NH 3 , the second precursor being free of H 2 .

18. The method of claim 12 , wherein

the first stress layer has a first Young's module; and

the second stress layer has a second Young's module less than the first Young's module.

19. The method of claim 12 , wherein

the first stress layer has a first thickness;

the second stress layer has a second thickness; and

the third stress layer has a third thickness, wherein the third thickness is less than the first thickness and the first thickness is less than the second thickness.

20. A method of forming an integrated circuit structure, the method comprising:

forming a first stress layer of a first compressive stress on a semiconductor substrate;

forming a second stress layer of a second compressive stress over the first stress layer;

forming a third stress layer of a tensile stress between the first and second stress layers; and

patterning the semiconductor substrate to form fin active regions using the first, second and third stress layers as an etch mask, wherein the second compressive stress is greater than the first compressive stress and the third stress layer includes amorphous silicon.