IP Library › Granted Patent US 11,061,612
Granted Patent B2
US 11,061,612 · App. 16/417,029 · Granted Jul 13, 2021

Internal communication interface management

Inventor: Sebastien Andre Jean (Meridian, ID)
Assignee: Micron Technology, Inc.
G06F3/0659G06F3/0604G06F3/0679G06F13/1668G06F2212/401G11C16/0483H03M7/30
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Quick Facts
Patent No.
US 11,061,612
App. No.
16/417,029
Filed
May 20, 2019
Granted
Jul 13, 2021
Kind
B2
Art Unit
2133
USPC
711/103
Abstract

Apparatus and methods are disclosed, including enabling communication between a memory controller and multiple memory devices of a storage system using a storage-system interface, the multiple memory devices each comprising a device controller and a group of non-volatile memory cells, and compressing data using at least one of the device controllers prior to transfer over the storage-system interface to improve an effective internal data transmission speed of the storage system.

Claims (60)

1. A storage system comprising:

a memory controller;

multiple memory devices, each comprising a device controller and a group of non-volatile memory cells; and

a storage-system interface configured to enable communication between the memory controller and one or more of the multiple memory devices,

wherein at least one of the device controllers is configured to:

selectively compress data prior to transfer over the storage-system interface to improve an effective internal data transmission speed of the storage system; and

provide, with transfer of compressed data over the storage-system interface, an indication to pad data to a boundary to omit padded bits from the storage-system interface and not increase an effective capacity of the storage system, the boundary determined to replace a difference between a size of the compressed data and a size of the compressed data when it is uncompressed, to maintain alignment after transfer and subsequent decompression.

2. The storage system of claim 1 , wherein the multiple memory devices comprises first and second memory devices,

wherein the first memory device comprises a first device controller and the second memory device comprises a second device controller,

wherein the first device controller is configured to compress data prior to transfer over the storage-system interface to improve the effective internal data transmission speed of the storage system, and

wherein the first memory device is configured to transfer the compressed data over the storage-system interface.

3. The storage system of claim 2 , wherein the first memory device is further configured to receive data from the memory controller, to compress the received data, to store the compressed data, and to flag the compressed data to indicate compression,

wherein the storage system is configured to receive a read command for the received data, and

wherein the first memory device is configured to provide the compressed data to the memory controller in response to the received read command.

4. The storage system of claim 3 , comprising:

a host device comprising a host processor and a group of volatile memory cells; and

a host interface separate from the storage-system interface configured to enable communication between the memory controller and the host device,

wherein the host device and the storage system reside in a mobile electronic device.

5. The storage system of claim 3 , wherein the memory controller is configured to receive a read command from a host device through a host interface, to receive compressed data from the first memory device associated with the read command, and to decompress the compressed data prior to transfer to the host device over the host interface, and

wherein the storage system is a single storage device.

6. The storage system of claim 1 , wherein the device controllers are configured to selectively compress data prior to transfer over the storage-system interface to improve the effective internal data transmission speed of the storage-system interface.

7. The storage system of claim 1 , wherein the device controllers are configured to selectively compress data prior to transfer over the storage-system interface to improve the effective internal data transmission speed of the storage system separate from increasing the effective capacity of the storage system.

8. The storage system of claim 1 , wherein the device controllers are configured to:

selectively compress data prior to transfer over the storage-system interface to improve the effective internal data transmission speed of the storage system separate from increasing the effective capacity of the storage system.

9. A method of improving an effective internal data transmission speed of a storage system, comprising:

enabling communication between a memory controller and one or more of multiple memory devices using a storage-system interface, the multiple memory devices each comprising a device controller and a group of non-volatile memory cells;

selectively compressing data, using at least one of the device controllers, prior to transfer over the storage-system interface to improve an effective internal data transmission speed of the storage system; and

providing, using the at least one of the device controllers and with transfer of compressed data over the storage-system interface, an indication to pad data to a boundary to omit padded bits from the storage-system interface and not increase an effective capacity of the storage system, the boundary determined to replace a difference between a size of the compressed data and a size of the co pressed data when it is uncompressed, to maintain alignment after transfer and subsequent decompression.

10. The method of claim 9 , wherein the multiple memory devices comprise a first memory device, the first memory device comprising a first device controller,

wherein compressing data comprises compressing data using the first device controller,

wherein the method comprises:

transferring the compressed data, using the first memory device, over the storage-system interface.

11. The method of claim 10 , comprising:

receiving data from the memory controller at the first memory device;

compressing the received data at the first memory device;

storing the compressed data at the first memory device;

flagging the compressed data at the first memory device to indicate compression;

receiving a read command at the first memory device; and

providing the compressed data from the first memory device to the memory controller in response to the received read command.

12. The method of claim 11 , comprising:

receiving a read command from a host device;

receiving compressed data from the first memory device associated with the read command; and

decompressing the received compressed data prior to transfer to the host device over a host interface separate from the storage-system interface.

13. The method of claim 9 , wherein compressing data comprises selectively compressing data prior to transfer over the storage-system interface to improve the effective internal data transmission speed of the storage system separate from increasing a clock speed or the effective capacity of the storage system.

14. The method of claim 9 , comprising:

enabling communication between the memory controller and a host device over a host interface separate from the storage-system interface.

15. A non-transitory device-readable storage: medium comprising instructions that, when executed by controller circuitry of a storage system, cause the storage system to perform operations comprising:

enabling communication between a memory controller and one or more of multiple memory devices of the storage system using a storage-system interface, the multiple memory devices each comprising a device controller and a group of non-volatile memory cells;

selectively compressing data, using at least one of the device controllers, prior to transfer over the storage-system interface to improve an effective internal data transmission speed of the storage system; and

providing, with transfer of compressed data over the storage-system interface, an indication to pad data to a boundary to omit padded bits from the storage-system interface and not increase an effective capacity of the storage system, the boundary determined to replace a difference between a size of the compressed data and a size of the compressed data when it is uncompressed, to maintain alignment after transfer and subsequent decompression.

16. The non-transitory device-readable storage medium of claim 15 , wherein the multiple memory devices comprises a first memory device, the first memory device comprising a first device controller,

wherein the operation to compress data prior to transfer over the storage-system interface comprises compressing data using the first, device controller prior to transfer over the storage-system interface, and

wherein the operations further comprise transferring the compressed data, using the first memory device, over the storage-system interface.

17. The non-transitory device-readable storage medium of claim 15 , wherein the operation to compress data prior to transfer over the storage-system interface comprises selectively compressing data prior to transfer over the storage-system interface to improve the effective internal data transmission speed of the storage system.

18. A storage system comprising:

a memory controller;

multiple memory devices, each comprising a device controller and a group of non-volatile memory cells; and

a storage-system interface configured to enable communication between the memory controller and the multiple memory devices,

wherein the memory controller is configured to provide, to a device controller of a memory device of the multiple memory devices, compressed data and an indication to pad data to a boundary to omit padded bits from the internal communication interface, the boundary determined to replace a difference between a size of the compressed data and a size of the compressed data when it is uncompressed, to maintain alignment after transfer and subsequent decompression, and

wherein, in response to the provided indication to pad data to the boundary, the memory device is configured to pad data to the boundary.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2019
From: JEAN, SEBASTIEN ANDRE
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050015/0925 →
Continuity (1)
Related Publication 20200371709A1 · Nov 26, 2020
Cited By (1)
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