Semiconductor package

1. A semiconductor package comprising:

a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer;

a semiconductor chip having an active surface on which connection pads are disposed, an inactive surface opposing the active surface and a passivation layer disposed on the active surface, the active surface being disposed on and facing the connection structure to face the connection structure; and

an encapsulant covering at least a portion of the semiconductor chip,

wherein the semiconductor chip includes a groove formed in the active surface, the groove exposes a top surface and a side surface of the passivation layer, and the groove has a shape in which a width of a region of at least a portion of an internal region located closer to a central portion of the semiconductor chip than the active surface is greater than a width of an entrance region.

2. The semiconductor package of claim 1 , wherein the groove is disposed between an edge of the semiconductor chip and the connection pads.

3. The semiconductor package of claim 1 , wherein the groove is continuously formed along an edge of the semiconductor chip.

4. The semiconductor package of claim 1 , wherein the groove includes a plurality of grooves continuously formed, respectively, along an edge of the semiconductor chip and separated from each other.

5. The semiconductor package of claim 1 , wherein the groove is formed in the active surface of the semiconductor chip and is recessed toward the inactive surface.

6. The semiconductor package of claim 1 , wherein the groove has a jar shape.

7. The semiconductor package of claim 1 , wherein the groove has a chamfered edge.

8. The semiconductor package of claim 1 , wherein the passivation layer covers the active surface.

9. The semiconductor package of claim 8 , wherein the groove penetrates through the passivation layer, and

wherein the passivation layer is interposed between the groove and the encapsulant.

10. The semiconductor package of claim 9 , wherein a region of the groove penetrating through the passivation layer has a predetermined width.

11. The semiconductor package of claim 1 , further comprising a frame disposed on the connection structure and having a through-hole accommodating the semiconductor chip.

12. The semiconductor package of claim 11 , wherein the encapsulant fills the through-hole, and covers the inactive surface and side surfaces of the semiconductor chip.

13. The semiconductor package of claim 12 , wherein the encapsulant covers a portion of the active surface of the semiconductor chip.

14. The semiconductor package of claim 1 , wherein the encapsulant is filled in at least a portion of the groove.

15. The semiconductor package of claim 14 , wherein a void is disposed inside the groove.

16. The semiconductor package of claim 15 , wherein the void is sealed by the encapsulant.

17. The semiconductor package of claim 1 , wherein the groove includes a plurality of sections each extending continuously between edges of the semiconductor chip and intersecting each other.

18. A semiconductor package comprising:

a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer;

a semiconductor chip having an active surface on which connection pads are disposed, an inactive surface opposing the active surface and a passivation layer disposed on the active surface, the active surface being disposed on and facing the connection structure; and

an encapsulant covering at least a portion of the semiconductor chip,

wherein the semiconductor chip includes a groove formed in the active surface that exposes a top surface and a side surface of the passivation layer.

19. The semiconductor package of claim 18 , wherein the groove has an entrance region formed in the active surface and penetrating through the passivation layer, a top region, and a middle region interposed between the entrance region and the top region, wherein a first width of the middle region is greater than a second width of the entrance region and a third width of the top region.

20. A semiconductor package comprising:

a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer;

a semiconductor chip having an active surface on which connection pads are disposed, an inactive surface opposing the active surface and a passivation layer disposed on the active surface, the active surface being disposed on and facing the connection structure, the semiconductor chip including a groove formed in the active surface that exposes a top surface and a side surface of the passivation layer and penetrates through the passivation layer, and the groove having an entrance region formed in the active surface and penetrating through the passivation layer, a top region, and a middle region interposed between the entrance region and the top region, wherein a first width of the middle region is greater than a second width of the entrance region and a third width of the top region; and

an encapsulant covering at least a portion of the semiconductor chip.