Inserting predefined pad values into a stream of vectors

1. A method of operating a streaming engine in a computer system, the method comprising:

receiving stream parameters into control logic of the streaming engine to define a multidimensional array, wherein the stream parameters define a size for each dimension of the multidimensional array and a pad value indicator;

fetching data from a memory coupled to the streaming engine responsive to the stream parameters;

forming a stream of vectors from the data fetched from memory for the multidimensional array responsive to the stream parameters;

forming a padded stream vector for the stream of vectors that includes a pad value specified by the pad value indicator without fetching respective pad data from the memory; and

suppressing a respective access to the memory while forming the padded stream vector.

2. The method of claim 1 , in which the stream parameters define a selected dimension of the multidimensional array, and in which the padded stream vector is formed in the selected dimension of the stream of vectors.

3. The method of claim 1 , in which the pad value indicator specifies one of a minimum value, a maximum value, or zero.

4. The method of claim 1 , in which the stream parameters include an element size of the array, a number of elements to include in each vector of a stream, and a number of vectors to include in the stream for each dimension of the array.

5. The method of claim 4 , in which the pad value forms a last element of the stream of vectors.

6. The method of claim 1 , further comprising suppressing access to an address lookaside buffer while forming the padded stream vector.

7. A system comprising:

a system memory;

a streaming engine coupled to the system memory, wherein the streaming engine comprises:

a stream template register to store stream parameters, wherein the stream parameters define a size for each dimension of a multidimensional array and a pad value indicator;

address generation logic coupled to the stream template register;

a memory interface logic coupled to receive a stream of addresses from the address generation logic and coupled to access the system memory; and

control logic coupled to the memory interface logic, wherein the control logic is configured to form a padded stream vector that includes a pad value specified by the pad value indicator without fetching respective pad data from the memory by suppressing a respective access to the system memory responsive to the stream parameters while forming the padded stream vector.

8. The system of claim 7 , further comprising a translation lookaside buffer coupled to the address generation logic, wherein the control logic is operable to suppress an access to the translation lookaside buffer by the address generation logic for forming the padded stream vector.

9. The system of claim 7 , in which all elements in the padded stream vector have a value of zero.

10. The system of claim 7 , in which an element in the padded stream vector has the pad value that is specified by the stream parameters to be one of a minimum value or a maximum value.

11. The system of claim 7 , further comprising:

a register file with outputs; and

an alignment network with inputs coupled to the outputs of the register file, the alignment network coupled to the control logic for control, the alignment network having outputs coupled to outputs of the streaming engine to provide the padded stream vector responsive to the pad value indicator.

12. The system of claim 7 being a system on a chip (SoC), further comprising a processing unit coupled to the outputs of the streaming engine to receive a stream of vectors.

13. A system comprising:

a system memory;

a streaming engine coupled to access the system memory, the streaming engine configured to:

receive stream parameters defining an array, wherein the stream parameters include:

a number of vectors for each dimension in the array; and

a pad value;

in response to receiving the stream parameters, generate an address stream based on the stream parameters;

for each dimension in the array:

retrieve, based on the address stream, one or more elements from the system memory; and

form the number of vectors for each dimension in the array, wherein each of the number of vectors is formed based on the one or more elements retrieved from the system memory; and

form a stream of vectors with the number of vectors for each dimension, wherein the streaming engine is operable to insert a padded vector having the pad value into the stream of vectors for each dimension; and

a processing unit coupled to outputs of the streaming engine to receive the stream of vectors for each dimension.

14. The system of claim 13 , in which the streaming engine comprises:

a stream template register to store the stream parameters; and

control logic coupled to receive the stream parameters from the stream template register.

15. The system of claim 14 , further comprising:

address generation logic configured to generate the address stream;

a memory interface logic coupled to receive the address stream from the address generation logic and coupled to access the system memory; and

wherein the control logic is operable to suppress an access to the system memory responsive to the stream parameters while forming the padded vector.

16. The system of claim 15 , further comprising a translation lookaside buffer coupled to the address generation logic, wherein the control logic is operable to suppress an access to the translation lookaside buffer by the address generation logic while forming the padded vector.

17. The system of claim 14 , further comprising:

a register file with inputs coupled to receive the one or more elements a vector fetched from the system memory; and

an alignment network with inputs coupled to outputs of the register file, the alignment network coupled to the control logic for control, the alignment network having outputs coupled to outputs of the streaming engine to provide the padded vector responsive to the stream parameters.

18. The system of claim 13 , in which all of the one or more elements in the padded vector have a value of zero.

19. The system of claim 13 , in which the pad value of the one or more elements in the padded vector is one of a minimum value and a maximum value.