Compilation flow for a heterogeneous multi-core architecture

1. A method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array, comprising:

determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels;

mapping, based on the graph representation, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array;

routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC; and

generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

2. The method of claim 1 , further comprising:

processing the graph representation to cluster the kernels into groups prior to the step of mapping;

wherein the step of mapping includes mapping at least one cluster of kernels onto one DPE in the DPE array.

3. The method of claim 1 , further comprising:

optimizing code of one or more of the kernels prior to the step of mapping.

4. The method of claim 1 , wherein the step of mapping comprises:

mapping the data structures onto at least one of memory banks in the DPEs and direct memory access (DMA) streams between DPEs.

5. The method of claim 1 , further comprising:

allocating locks for DPE-to-DPE communication in the DPE array.

6. The method of claim 1 , wherein the step of generating the implementation data comprises:

generating code for each DPE to implement one or more of the kernels therein.

7. The method of claim 1 , wherein the step of generating the implementation data comprises:

generating control code to configure direct memory access (DMA) and switch circuitry in the DPE array.

8. A non-transitory computer readable medium having stored thereon instructions that when executed by a processor cause the processor to perform a method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array, the method comprising:

determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels;

mapping, based on the graph representation, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array;

routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC; and

generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

9. The non-transitory computer readable medium of claim 8 , further comprising:

processing the graph representation to cluster the kernels into groups prior to the step of mapping;

wherein the step of mapping includes mapping at least one cluster of kernels onto one DPE in the DPE array.

10. The non-transitory computer readable medium of claim 8 , further comprising:

optimizing code of one or more of the kernels prior to the step of mapping.

11. The non-transitory computer readable medium of claim 8 , wherein the step of mapping comprises:

mapping the data structures onto at least one of memory banks in the DPEs and direct memory access (DMA) streams between DPEs.

12. The non-transitory computer readable medium of claim 8 , further comprising:

allocating locks for DPE-to-DPE communication in the DPE array.

13. The non-transitory computer readable medium of claim 8 , wherein the step of generating the implementation data comprises:

generating code for each DPE to implement one or more of the kernels therein.

14. The non-transitory computer readable medium of claim 8 , wherein the step of generating the implementation data comprises:

generating control code to configure direct memory access (DMA) and switch circuitry in the DPE array.

15. A computer system, comprising:

a memory configured to store program code; and

a processor configured to execute the program code to implement an application for a system-on-chip (SOC) having a data processing engine (DPE) array by:

determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels;

mapping, based on the graph representation, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array;

routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC; and

generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

16. The computer system of claim 15 , further comprising:

processing the graph representation to cluster the kernels into groups prior to the step of mapping;

wherein the step of mapping includes mapping at least one cluster of kernels onto one DPE in the DPE array.

17. The computer system of claim 15 , further comprising:

optimizing code of one or more of the kernels prior to the step of mapping.

18. The computer system of claim 15 , wherein the step of mapping comprises:

mapping the data structures onto at least one of memory banks in the DPEs and direct memory access (DMA) streams between DPEs.

19. The computer system of claim 15 , wherein the step of generating the implementation data comprises:

generating code for each DPE to implement one or more of the kernels therein.

20. The computer system of claim 15 , wherein the step of generating the implementation data comprises:

generating control code to configure direct memory access (DMA) and switch circuitry in the DPE array.