IP Library › Granted Patent US 10,872,057
Granted Patent B1
US 10,872,057 · App. 16/420,927 · Granted Dec 22, 2020

Partitioning in a compiler flow for a heterogeneous multi-core architecture

Inventors: Prashant S. Rawat (San Jose, CA); Shail Aditya Gupta (San Jose, CA)
Assignee: XILINX, INC.
G06F15/7807G06F9/4881
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Quick Facts
Patent No.
US 10,872,057
App. No.
16/420,927
Granted
Dec 22, 2020
Kind
B1
Abstract

An example method of placing kernels of an application in a data processing engine array (DPE) of a system on chip (SOC) includes obtaining a graph of the application having nodes representing the kernels and edges representing communication between the kernels, sorting the kernels based on runtime ratio associated with each of the kernels, processing the sorted kernels sequentially to place into partitions, determining an execution order of kernels in each of the partitions; and generating implementation data for the SOC for implementing the application therein based on the determined partitions and execution order for each of the partitions.

Claims (46)

1. A method of placing kernels of an application in a data processing engine array (DPE) of a system on chip (SOC), comprising:

obtaining a graph of the application having nodes representing the kernels and edges representing communication between the kernels;

sorting the kernels based on runtime ratio associated with each of the kernels;

processing the sorted kernels sequentially to place into partitions;

determining an execution order of kernels in each of the partitions; and

generating implementation data for the SOC for implementing the application therein based on the determined partitions and execution order for each of the partitions.

2. The method of claim 1 , further comprising:

grouping a portion of the kernels into initial partitions based on user-defined constraints.

3. The method of claim 2 , wherein the portion of the kernels is grouped into the initial partitions based on at least one of an absolute constraint and a relative constraint in the user-defined constraints.

4. The method of claim 1 , wherein the step of processing the sorted kernels comprises:

maintaining a cumulative runtime ratio of each partition to be less than or equal to a threshold value.

5. The method of claim 1 , wherein the step of processing the sorted kernels comprises:

updating location constraints of each partition based on respective kernels assigned thereto.

6. The method of claim 5 , wherein the step of updating the location constraints of each partition comprises:

updating the location constraints of a first partition of the partitions based on at least one of an absolute constraint assigned to the kernel, a physical constraint of the data processing engine array, and a dynamic constraint resulting from the step of processing the sorted kernels.

7. The method of claim 1 , wherein the step of processing the sorted kernels comprises:

satisfying physical constraints of the DPE array.

8. The method of claim 7 , wherein the physical constraints comprise at least one of a defined number of input/output ports for each partition and a defined type of connection between kernels within each partition.

9. The method of claim 1 , wherein the step of processing the sorted kernels comprises:

satisfying one or more dynamic location constraints arising from placement of kernels into the partitions.

10. The method of claim 1 , wherein the step of processing the sorted kernels comprises:

placing a first kernel of the kernels into an existing partition of the partitions or a new partition added to the partitions, where selection of the existing partition or the new partition is based on constraints of the first kernel and constraints of one or more kernels in the existing partition.

11. The method of claim 1 , further comprising:

performing post-partitioning optimizations for communication minimization among the kernels.

12. A computer system, comprising:

a memory configured to store program code; and

a processor configured to execute the program code to place kernels of an application in a data processing engine array (DPE) of a system on chip (SOC) by:

obtaining a graph of the application having nodes representing the kernels and edges representing communication between the kernels;

sorting the kernels based on runtime ratio associated with each of the kernels;

processing the sorted kernels sequentially to place into partitions;

determining an execution order of kernels in each of the partitions; and

generating implementation data for the SOC for implementing the application therein based on the determined partitions and execution order for each of the partitions.

13. The computer system of claim 12 , further comprising:

grouping a portion of the kernels into initial partitions based on user-defined constraints.

14. The computer system of claim 13 , wherein the portion of the kernels is grouped into the initial partitions based on at least one of an absolute constraint and a relative constraint in the user-defined constraints.

15. The computer system of claim 12 , wherein the processing the sorted kernels comprises:

maintaining a cumulative runtime ratio of each partition to be less than or equal to a threshold value.

16. The computer system of claim 12 , wherein the processing the sorted kernels comprises:

updating location constraints of each partition based on respective kernels assigned thereto.

17. The computer system of claim 16 , wherein the updating the location constraints of each partition comprises:

updating the location constraints of a first partition of the partitions based on at least one of an absolute constraint assigned to the kernel, a physical constraint of the data processing engine array, and a dynamic constraint resulting from the step of processing the sorted kernels.

18. The computer system of claim 12 , wherein the processing the sorted kernels comprises:

satisfying physical constraints of the DPE array.

19. The computer system of claim 18 , wherein the physical constraints comprise at least one of a defined number of input/output ports for each partition and a defined type of connection between kernels within each partition.

20. The computer system of claim 16 , wherein the processing the sorted kernels comprises:

satisfying one or more dynamic location constraints arising from placement of kernels into the partitions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2019
From: RAWAT, PRASHANT S.; GUPTA, SHAIL ADITYA
To: XILINX, INC.
Reel/Frame 049273/0526 →
Cited By (2)
US 12,332,837 US 12,591,539