Transistor device and related methods

1. A method, comprising:

providing a device including a gate stack having a metal gate layer, a spacer layer disposed on a sidewall of the gate stack, and a source/drain feature adjacent to the gate stack;

performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer;

depositing a metal layer over the etched-back metal gate layer; and

forming a semiconductor layer over both the metal layer and the spacer layer, wherein the semiconductor layer provides a T-shaped helmet layer over the gate stack and the spacer layer.

2. The method of claim 1 , wherein the depositing the metal layer over the etched-back metal gate layer further includes depositing a fluorine-free tungsten (FFW) layer over the etched-back metal gate layer.

3. The method of claim 1 , wherein the forming the semiconductor layer over both the metal layer and the spacer layer further includes forming one of a silicon nitride (SiN) layer and an amorphous silicon (a-Si) layer over both the metal layer and the spacer layer.

4. The method of claim 1 , further comprising:

prior to the forming the semiconductor layer over both the metal layer and the spacer layer, conformally depositing a liner layer over the metal layer and on a portion of the spacer layer.

5. The method of claim 4 , wherein the depositing the liner layer further includes depositing a high-K liner layer.

6. The method of claim 4 , wherein the liner layer prevents etching of the metal layer and the spacer layer during a subsequent etching process.

7. The method of claim 1 , further comprising:

performing a second etch-back process to the semiconductor layer to form an etched-back semiconductor layer; and

forming a dielectric layer over the etched-back semiconductor layer.

8. The method of claim 1 , further comprising:

depositing a contact metal layer over the source/drain feature;

etching back the contact metal layer to provide an etched-back contact metal layer; and

depositing a contact etch stop layer (CESL) over the etched-back contact metal layer.

9. The method of claim 8 , further comprising:

after forming the semiconductor layer over both the metal layer and the spacer layer, replacing the semiconductor layer with a low-K dielectric layer.

10. The method of claim 8 , further comprising:

prior to depositing the CESL, forming a cap layer over the etched-back contact metal layer, wherein the cap layer prevents oxidation of the etched-back contact metal layer.

11. A method, comprising:

providing a device including a gate stack having an etched-back metal gate layer and etched-back spacer layers disposed on opposing sidewalls of the gate stack, wherein the etched-back metal gate layer and the etched-back spacer layers collectively define a T-shaped opening;

depositing a fluorine-free tungsten (FFW) layer over the etched-back metal gate layer; and

forming a helmet layer over the FFW layer and within the T-shaped opening such that the helmet layer defines a T-shaped helmet layer.

12. The method of claim 11 , wherein the forming the helmet layer further includes forming one of a silicon nitride (SiN) layer and an amorphous silicon (a-Si) layer over the FFW layer and within the T-shaped opening.

13. The method of claim 11 , further comprising:

prior to the forming the helmet layer, depositing a high-K liner layer over the FFW layer and along sidewalls of the T-shaped opening; and

forming the helmet layer over the high-K liner layer.

14. The method of claim 11 , further comprising:

etching-back the helmet layer to form an etched-back helmet layer; and

depositing a high-K dielectric layer over the etched-back helmet layer.

15. The method of claim 14 , further comprising:

depositing a contact metal layer over a source/drain feature adjacent to the gate stack; and

performing a chemical mechanical polishing (CMP) process to remove a portion of the contact metal layer, wherein the CMP process also removes the high-K dielectric layer.

16. The method of claim 15 , further comprising:

after performing the CMP process, forming a cap layer over the contact metal layer, wherein the cap layer prevents oxidation of the contact metal layer; and

depositing a contact etch stop layer (CESL) over the cap layer.

17. The method of claim 15 , further comprising:

after performing the CMP process, replacing the helmet layer with a low-K dielectric layer.

18. A method, comprising:

forming a T-shaped opening over a gate structure, wherein a bottom surface of the T-shaped opening is defined by an etched-back metal gate layer, and wherein sidewall surfaces of the T-shaped opening are at least partially defined by sidewall spacers;

depositing a metal layer in contact with the etched-back metal gate layer, wherein the sidewall surfaces of the T-shaped opening are substantially free of the metal layer; and

depositing a silicon (Si)-based layer within the T-shaped opening and in contact with both the bottom surface and the sidewall surfaces of the T-shaped opening, wherein the Si-based layer defines a T-shaped helmet layer.

19. The method of claim 18 , further comprising:

depositing a high-K dielectric layer over the T-shaped helmet layer; and

forming a source/drain contact opening adjacent to the gate structure, wherein the forming the source/drain contact opening at least partially etches the high-K dielectric layer, and wherein the high-K dielectric layer prevents etching of the T-shaped helmet layer.

20. The method of claim 19 , further comprising:

depositing a contact metal layer within the source/drain contact opening and in contact with a source/drain feature; and

forming a metal cap layer over the contact metal layer.