IP Library › Granted Patent US 10,963,247
Granted Patent B2
US 10,963,247 · App. 16/422,688 · Granted Mar 30, 2021

Vector floating-point classification

Inventors: Joseph Zbiciak (San Jose, CA); Brett L. Huber (Sugar Land, TX); Duc Bui (Grand Prairie, TX)
Assignee: Texas Instruments Incorporated
G06F9/30036G06F9/3013G06K9/6267
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,963,247
App. No.
16/422,688
Granted
Mar 30, 2021
Kind
B2
Abstract

A method to classify source data in a processor in response to a vector floating-point classification instruction includes specifying, in respective fields of the vector floating-point classification instruction, a source register containing the source data and a destination register to store classification indications for the source data. The source register includes a plurality of lanes that each contains a floating-point value and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector floating-point classification instruction by, for each lane in the source register, classifying the floating-point value in the lane to identify a type of the floating-point value, and storing a value indicative of the identified type in the corresponding lane of the destination register.

Claims (56)

1. A method to classify source data in a processor in response to a vector floating-point classification instruction, the method comprising:

receiving the vector floating-point classification instruction, wherein the vector floating-point classification instruction includes:

a source register field that specifies a source register containing the source data, wherein the source register comprises a plurality of lanes that each contains a floating-point value;

a destination register field that specifies a destination register to store classification indications for the source data, wherein the destination register comprises a plurality of lanes corresponding to the lanes of the source register; and

a third field that specifies a datapath from among a scalar datapath and a vector datapath to execute the vector floating-point classification instruction; and

executing the vector floating-point classification instruction by the datapath specified by the third field, wherein executing the vector floating-point classification instruction further comprises, for each lane in the source register:

classifying the floating-point value in the lane to identify a type of the floating-point value; and

storing a value indicative of the identified type in the corresponding lane of the destination register.

2. The method of claim 1 , wherein the source data comprises a 512-bit vector.

3. The method of claim 1 , wherein each floating-point value comprises a single precision floating-point value.

4. The method of claim 1 , wherein each floating-point value comprises a double precision floating-point value.

5. The method of claim 1 , wherein the type comprises one selected from the group consisting of: a zero value, a subnormal value, a normal value, an infinite value, a not a number (NaN) value, a quiet NaN (QNaN), and a signaling NaN (SNaN).

6. The method of claim 5 , further comprising:

storing a value of 0 in the corresponding lane of the destination register in response to the identified type being a zero value;

storing a value of 1 in the corresponding lane of the destination register in response to the identified type being a subnormal value;

storing a value of 2 in the corresponding lane of the destination register in response to the identified type being a normal value;

storing a value of 3 in the corresponding lane of the destination register in response to the identified type being an infinite value;

storing a value of 4 in the corresponding lane of the destination register in response to the identified type being a NaN value; and

storing a value of 8 in the corresponding lane of the destination register in response to the identified type being a SNaN value.

7. A data processor, comprising:

a scalar datapath;

a vector datapath coupled in parallel with the scalar datapath;

a source register configured to contain source data; and

a destination register;

wherein the source register comprises a plurality of lanes that each contain a floating-point value and the destination register comprises a plurality of lanes corresponding to the lanes of the source register;

wherein, in response a single vector floating-point classification instruction that specifies a datapath from among the scalar datapath and the vector datapath, the datapath of the data processor is configured to, for each lane in the source register:

classify the floating-point value in the lane to identify a type of the floating-point value; and

store a value indicative of the identified type in the corresponding lane of the destination register.

8. The data processor of claim 7 , wherein the source data comprises a 512-bit vector.

9. The data processor of claim 7 , wherein each floating-point value comprises a single precision floating-point value.

10. The data processor of claim 7 , wherein each floating-point value comprises a double precision floating-point value.

11. The data processor of claim 7 , wherein the type comprises one selected from the group consisting of: a zero value, a subnormal value, a normal value, an infinite value, a not a number (NaN) value, a quiet NaN (QNaN), and a signaling NaN (SNaN).

12. The data processor of claim 11 , wherein, in response to execution of a single vector floating-point classification instruction, the data processor is further configured to, for each lane in the source register:

store a value of 0 in the corresponding lane of the destination register in response to the identified type being a zero value;

store a value of 1 in the corresponding lane of the destination register in response to the identified type being a subnormal value;

store a value of 2 in the corresponding lane of the destination register in response to the identified type being a normal value;

store a value of 3 in the corresponding lane of the destination register in response to the identified type being an infinite value;

store a value of 4 in the corresponding lane of the destination register in response to the identified type being a NaN value; and

store a value of 8 in the corresponding lane of the destination register in response to the identified type being a SNaN value.

13. The method of claim 1 , wherein the vector floating-point classification instruction includes a fourth field that specifies a functional unit of the datapath to perform the vector floating-point classification.

14. The method of claim 1 , wherein the third field of the vector floating-point classification instruction specifies the scalar datapath.

15. The method of claim 1 , wherein:

each of the floating-point values includes a respective exponent and a respective fraction; and

the executing of the vector floating-point classification includes determining the type of each of the floating-point values based on the respective exponent and the respective fraction.

16. The method of claim 15 , wherein:

each of the floating-point values further includes a respective sign; and

the executing of the vector floating-point classification includes determining the type of each of the floating-point values further based on the respective sign.

17. The data processor of claim 7 , wherein:

the single vector floating-point classification instruction further specifies a functional unit of the datapath; and

the functional unit of the datapath is configured to classify the floating-point values and store the values indicative of the identified types in response to the single vector floating-point classification instruction.

18. The data processor of claim 7 , wherein:

each of the floating-point values includes a respective exponent and a respective fraction; and

the datapath is configured to determine the type of each of the floating-point value based on the respective exponent and the respective fraction.

19. The data processor of claim 18 , wherein:

each of the floating-point values further includes a respective sign; and

the datapath is configured to determine the type of each of the floating-point value further based on the respective sign.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2019
From: ZBICIAK, JOSEPH; HUBER, BRETT L.; BUI, DUC
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 049281/0650 →
Continuity (1)
Related Publication 20200371794A1 · Nov 26, 2020
Cited By (1)
US 12,730,635