Performing data restore operations in memory

1. An apparatus, comprising:

a memory; and

a controller configured to:

perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein:

the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory; and

the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory; and

invert a value of a global phase bit associated with the memory upon initiating the performance of the data restore operation, such that the inverted value of the global phase bit does not match a value of a phase bit associated with the data stored in the memory.

2. The apparatus of claim 1 , wherein the controller is configured to perform the data restore operation on the data stored in the memory by:

performing a sense operation on the memory using the current mapping of the data included in the first table; and

performing a program operation on the memory using the new mapping of the data included in the second table.

3. The apparatus of claim 1 , wherein:

the current mapping of the data included in the first table includes a mapping of the data to a first physical location in the memory; and

the new mapping of the data included in the second table includes a mapping of the data to a second physical location in the memory that is different than the first physical location.

4. The apparatus of claim 3 , wherein the second physical location has a lower error rate associated therewith than the first physical location.

5. The apparatus of claim 3 , wherein the second physical location is a spare location in the memory.

6. The apparatus of claim 1 , wherein the first table and the second table are stored in non-volatile memory of the controller.

7. The apparatus of claim 1 , further comprising the controller configured to:

determine to use the current mapping to sense the data stored in the memory based on a value of the phase bit associated with the data stored in the memory; and

determine to use the new mapping to program the sensed data to the memory based on the value of the phase bit.

8. An apparatus, comprising:

a memory; and

a controller configured to:

rank groups of data stored in the memory based on a first error rate associated with each respective group;

generate a first table that includes a mapping of the groups of data that is based on the ranking;

re-rank the groups of data based on a second error rate associated with each respective group determined subsequent to generating the first table;

generate a second table that includes a mapping of the groups of data that is based on the re-ranking;

perform a data restore operation on the groups of data;

perform an additional re-ranking of the groups of data based on a third error rate associated with each respective group determined subsequent to performing the data restore operation;

update the mapping of the groups of data in the first table based on the additional re-ranking; and

perform an additional data restore operation on the groups of data based on the updated mapping, wherein

the first table and the second table each include a plurality of entries, wherein each respective entry corresponds to a different one of the plurality of groups of data; and

each respective entry includes:

a logical address for its respective group of data; and

a physical address for its respective group of data.

9. The apparatus of claim 8 , further comprising the controller configured to determine the first error rate, the second error rate, and the third error rate.

10. The apparatus of claim 8 , further comprising the controller configured to:

sense each respective group of data using the mapping of the second table; and

program the sensed data to the memory using the updated mapping of the first table.

11. The apparatus of claim 10 , further comprising the controller configured to program the sensed data to a physical location in the memory that is different from a physical location in the memory from which the data is sensed and has a lower error rate associated therewith than the physical location in the memory from which the data is sensed.

12. The apparatus of claim 10 , further comprising the controller configured to:

determine to use the mapping of the second table to sense each respective group of data based on a value of a phase bit associated with the data stored in the memory; and

determine to use the updated mapping to program the sensed data to the memory based on the value of the phase bit.

13. The apparatus of claim 8 , further comprising the controller configured to perform sequential sense operations to sequentially sense each respective group of data using the mapping of the groups of data included in the second table.

14. The apparatus of claim 13 , wherein the entry in the second table corresponding to a particular one of the groups of data includes:

a same logical address as the logical address for that group in the entry in the first table corresponding to that group; and

a different physical address than the physical address for that group in the entry in the first table corresponding to that group.

15. A method for operating memory, comprising:

performing a data restore operation on data stored in a memory by:

sensing the data stored in the memory using a first mapping of the data, wherein:

the first mapping is a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data; and

the first mapping is stored in a first table; and

programming the sensed data to the memory using a second mapping of the data, wherein:

the second mapping is new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data; and

the second mapping is stored in a second table;

detecting a power loss while performing the data restore operation; and

storing, upon detecting the power loss, a value of a phase bit and a logical address for the data stored in the memory upon which the data restore operation has most recently been performed.

16. The method of claim 15 , further comprising inverting the value of the phase bit associated with the data store in memory upon programming the sensed data to the memory.

17. The method of claim 15 , further comprising:

performing sequential sense operations to sequentially sense portions of the data using the second mapping; and

performing, upon the sense operation to sense a portion of the data failing, a sense operation to sense that portion of the data using the first mapping; and

resuming the data restore operation upon the sense operation to sense that portion of the data using the first mapping succeeding.