Method of manufacturing a semiconductor device
A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH 3 ) and at least one of arsine (AsH 3 ) or monomethylsilane (CH 6 Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.
1. A method comprising:
etching a semiconductor fin to form a first recess and a second semiconductor fin to form a second recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction;
forming a source/drain region in the first recess, the source/drain region comprising a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region comprising phosphine (PH 3 ) and at least one of arsine (AsH 3 ) or monomethylsilane (CH 6 Si), a local maximum width of the source/drain region above a top surface of the semiconductor fin being less than a local maximum width of the source/drain region below the top surface of the semiconductor fin, the single continuous material comprising SiP:C:As;
forming a second source/drain region in the second recess, the second source/drain region comprising the single continuous material, wherein the single continuous material of the second source/drain region merges with the single continuous material of the source/drain region; and
forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.
2. The method of claim 1 , wherein the source/drain region is formed in an NMOS region of a semiconductor device.
3. The method of claim 1 , wherein the source/drain region is formed at a temperature from 400° C. to 800° C.
4. The method of claim 1 , wherein the source/drain region is formed at a pressure from 5 torr to 600 torr.
5. The method of claim 1 , wherein the first recess has a depth from 35 to 60 nm below the top surface of the semiconductor fin and a width from 20 to 35 nm.
6. The method of claim 1 , wherein the source/drain region has a phosphorus concentration from 1×10 21 to 5×10 21 atoms/cm 3 and a carbon concentration from 0.1 to 2 atomic percent.
7. The method of claim 1 , wherein the source/drain region has a phosphorus concentration from 1×10 21 to 5×10 21 atoms/cm 3 and an arsenic concentration from 1×10 20 to 3×10 21 atoms/cm 3 .
8. A method comprising:
forming a fin extending from a substrate;
forming a gate stack over the fin;
forming a gate seal spacer along a sidewall of the gate stack;
forming a lightly doped source/drain (LDD) region in the fin using the gate stack and the gate seal spacer as a mask, the LDD region comprising silicon doped with phosphorous;
forming a gate spacer over the LDD region along a sidewall of the gate seal spacer;
etching the fin to form a first recess, the first recess extending under the gate spacer in a direction perpendicular to a major surface of the substrate; and
epitaxially depositing a source/drain material in the first recess, the source/drain material comprising SiP doped with arsenic, the source/drain material extending under the gate spacer in the direction perpendicular to the major surface of the substrate, the source/drain material contacting a vertical surface of the fin, wherein a first width of the source/drain material in a direction parallel to the major surface of the substrate at a point level with a top surface of the fin is less than a second width of the source/drain material in the direction parallel to the major surface of the substrate at a point below the top surface of the fin, wherein the source/drain material is in contact with a horizontal surface of the fin, a vertical surface of the gate seal spacer, the gate spacer, and the LDD region.
9. The method of claim 8 , wherein the source/drain material has a phosphorus concentration from 1×10 21 to 5×10 21 atoms/cm 3 and an arsenic concentration from 1×10 20 to 3×10 21 atoms/cm 3 .
10. The method of claim 8 , wherein the source/drain material further comprises carbon, and wherein the source/drain material has a phosphorus concentration from 1×10 21 to 5×10 21 atoms/cm 3 and a carbon concentration from 0.1 to 2 atomic percent.
11. The method of claim 10 , wherein the source/drain material has an arsenic concentration from 1×10 20 to 3×10 21 atoms/cm 3 .
12. The method of claim 8 , further comprising forming a silicide region at a top surface of the source/drain material, the silicide region having a thickness from 2 nm to 10 nm.
13. The method of claim 12 , wherein the silicide region comprises TiSi.
14. The method of claim 13 , further comprising forming a source/drain contact in contact with the silicide region, the source/drain contact extending into the source/drain material from 5 nm to 15 nm below a top surface of the source/drain material.
15. The method of claim 14 , wherein the source/drain contact comprises tungsten.
16. A method comprising:
forming a dummy gate structure over a semiconductor fin, the dummy gate structure comprising a dummy dielectric layer on the semiconductor fin;
forming a gate seal spacer on a sidewall of the dummy gate structure;
forming a gate spacer on a sidewall of the gate seal spacer;
etching the semiconductor fin to form a recess using the gate spacer as a mask;
forming a source/drain region in the recess, the source/drain region comprising a semiconductor material, the semiconductor material comprising SiP doped with arsenic and carbon, the SiP doped with arsenic and carbon contacting the semiconductor fin along sidewalls and a bottom surface of the recess, a first width of the source/drain region below a top surface of the semiconductor fin being greater than a second width of the source/drain region level with the top surface of the semiconductor fin, the first width and the second width being measured between vertical sidewalls of the source/drain region, wherein the SiP doped with arsenic and carbon further contacts a vertical sidewall of the dummy dielectric layer, a vertical sidewall and a horizontal surface of the gate seal spacer, and a sidewall of the gate spacer;
replacing at least a portion of the dummy gate structure with a gate over the semiconductor fin adjacent the source/drain region;
forming a silicide region in the source/drain region; and
forming a source/drain contact extending into the silicide region.
17. The method of claim 16 , wherein the silicide region comprises TiSi and the source/drain contact comprises tungsten.
18. The method of claim 16 , wherein the source/drain region has a phosphorus concentration from 1×10 21 to 5×10 21 atoms/cm 3 , an arsenic concentration from 1×10 20 to 3×10 21 atoms/cm 3 , and a carbon concentration from 0.1 to 2 atomic percent.
19. The method of claim 16 , wherein the source/drain region is formed using a first precursor comprising at least one of silane (SiH 4 ), dichlorosilane (SiH 2 Cl 2 ), or disilane (Si 2 H 6 ) and a second precursor comprising phosphine (PH 3 ), arsine (AsH 3 ), and monomethylsilane (CH 6 Si).
20. The method of claim 16 , wherein the source/drain region is formed at a temperature from 400° C. to 800° C. and a pressure of 5 torr to 600 torr.