Power semiconductor device and manufacturing method thereof

1. A power semiconductor device comprising:

a first trench gate and a second trench gate in a stripe shape extending in one direction in parallel and spaced apart from each other in a substrate;

a third trench gate in a ladder shape extending in a direction different from the one direction between the first trench gate and the second trench gate in the substrate;

a first conductive type body area each disposed between the first trench gate, the second trench gate and the third trench gate, respectively, in the substrate;

a pair of first conductive type floating first areas surrounding each of bottom surfaces and at least one side of the first trench gate and the second trench gate in the substrate;

a first conductive type floating second area surrounding a bottom surface of the third trench gate in the substrate;

an emitter electrode disposed on an upper surface of the substrate and in contact with the first conductive type body area; and

a collector electrode disposed on a bottom surface of the substrate.

2. The power semiconductor device of claim 1 , wherein a first trench gate and a second trench gate constituting one unit cell are connected to a first trench gate and a second trench gate constituting another unit cell immediately adjacent to the one unit cell without being separated from each other.

3. The power semiconductor device of claim 2 , wherein in a plurality of unit cells disposed in series being adjacent to each other, the first trench gates are connected as one and provided across the plurality of unit cells, the second trench gates are connected as one and provided across the plurality of unit cells, and the third trench gate is provided as a plurality of trench gates connecting one of the first trench gates and one of the second trench gates and spaced apart from each other between one of the first trench gates and one of the second trench gates.

4. The power semiconductor device of claim 1 , further comprising a second conductive type drift area disposed between the first conductive type floating area, the first conductive type body area, and the collector electrode in the substrate.

5. The power semiconductor device of claim 4 , further comprising a second conductive type field stop area disposed between the second conductive type drift area and the collector electrode.

6. The power semiconductor device of claim 1 , further comprising a pair of second conductive type source areas spaced apart from each other and respectively adjacent to the first trench gate and the second trench gate in a first conductive type body area disposed between the first trench gate and the second trench gate.

7. The power semiconductor device of claim 1 , wherein a doping maximum depth of the first conductive type body area disposed between the first trench gate and the second trench gate is shallower than a depth of the first trench gate and the second trench gate, and a doping maximum depth of the floating first area of the first conductive type is deeper than a depth of the first trench gate and the second trench gate.

8. The power semiconductor device of claim 7 , wherein a second conductive type doping concentration between the pair of first conductive type floating first areas and between the first trench gate and the second trench gate is relatively higher than a second conductive type doping concentration below the pair of first conductive type floating first areas in the drift area.

9. The power semiconductor device of any one of claims 1 to 8 , wherein the second conductive type and the first conductive type have a conductive type opposite to each other, and are any one of n-type and p-type.