Low power flip-flop circuit
Aspects for a flip-flop circuit are described herein. As an example, the aspects may include a passgate, a passgate inverter, a leakage compensation unit, and an inverter. The passgate may be coupled between a flip-flop data input terminal and a first node. The passgate inverter and the inverter may be sequentially connected between the first node and a flip-flop data output terminal. The leakage compensation unit may be connected between the first node and the flip-flop data output terminal parallel to the passgate inverter and the inverter.
1. A flip-flop circuit, comprising:
a flip-flop data input terminal and a flip-flop data output terminal;
a clock terminal that provides a first clock signal and a second clock signal, wherein the second clock signal is an inverse of the first clock signal;
a passgate coupled between the flip-flop data input terminal and a first node, wherein
the passgate includes a first P-channel gate terminal and a first N-channel gate terminal, and
the first P-channel gate terminal and the first N-channel gate terminal are respectively connected to the first clock signal and the second clock signal;
a passgate inverter coupled between the first node and a second node,
wherein the passgate inverter includes a first P-channel transistor, a second P-channel transistor, a first N-channel transistor, and a second N-channel transistor,
wherein the first P-channel transistor and the second N-channel transistor are connected to the first node,
wherein the second P-channel transistor is connected to the second clock signal, and
wherein the first N-channel transistor is connected to the first clock signal;
an inverter coupled between the second node and the flip-flop data output terminal; and
one or more leakage compensation units coupled between the first node and the flip-flop data output terminal,
wherein each of the one or more leakage compensation units includes a third P-channel transistor and a third N-channel transistor,
wherein gate terminals of the third P-channel transistor and the third N-channel transistor are connected to the flip-flop data output terminal.
2. The flip-flop circuit of claim 1 , wherein a gate terminal of the first P-channel transistor is connected to the first node.
3. The flip-flop circuit of claim 1 , wherein a gate terminal of the second N-channel transistor is connected to the first node.
4. The flip-flop circuit of claim 1 , wherein a gate terminal of the second P-channel transistor is connected to the second clock signal.
5. The flip-flop circuit of claim 1 , wherein a gate terminal of the first N-channel transistor is connected to the first clock signal.
6. The flip-flop circuit of claim 1 ,
wherein the third P-channel transistor is connected to the first node, and
wherein the third N-channel transistor is connected to the flip-flop data output terminal.
7. The flip-flop circuit of claim 1 ,
wherein the third N-channel transistor is connected to the first node, and
wherein the third P-channel transistor is connected to the flip-flop data output terminal.
8. The flip-flop circuit of claim 1 ,
wherein drain terminals of the third P-channel transistor and the third N-channel transistor are connected to the first node,
wherein the third N-channel transistor is connected to the first node, and
wherein the third P-channel transistor is connected to the flip-flop data output terminal.
9. The flip-flop circuit of claim 1 ,
wherein the drain terminals of the third P-channel transistor and the third N-channel transistor are connected to the first node,
wherein the third P-channel transistor is connected to the first node, and
wherein the third N-channel transistor is connected to the flip-flop data output terminal.
10. The flip-flop circuit of claim 1 , wherein the one or more leakage compensation units are connected sequentially.
11. The flip-flop circuit of claim 1 , wherein the one or more leakage compensation units are connected parallelly.