Selection circuit

1. A voltage selection comprising:

a first device and a second device connected to output an output signal, wherein the voltage selection circuit is configured to output a higher voltage of a first supply voltage and a second supply voltage through one of the first device and the second device, and wherein a voltage difference between the first supply voltage and the second supply voltage is less than a threshold voltage; and

a third device comprising an NWELL having a same voltage potential as the output signal.

2. The voltage selection circuit of claim 1 , wherein the first device is a PMOS transistor which has a source at the voltage potential of the first supply voltage.

3. The voltage selection circuit of claim 2 , wherein the second device is a PMOS transistor which has a source at the voltage potential of the second supply voltage.

4. The voltage selection circuit of claim 3 , wherein:

a drain of the first device is connected to a drain of the second device and;

the drain of the first device and the drain of the second device provide the output signal.

5. The voltage selection circuit of claim 4 , wherein the third device comprises:

a source at a same voltage potential as the second supply voltage;

a gate at a same voltage potential as the first supply voltage; and

a drain connected to a gate of a fourth device.

6. The voltage selection circuit of claim 4 , further comprising a fourth device comprising:

an NWELL at a same voltage potential as the output signal;

a source at a same voltage potential as the first supply voltage;

a gate at a same voltage potential as the second supply voltage; and

a drain connected to a gate of the third device.

7. The voltage selection circuit of claim 6 , further comprising a gate bias circuitry which includes:

a fifth device with an NWELL at the same voltage potential as the output signal and a source at the same voltage potential as the first supply voltage; and

a sixth device with an NWELL at the same voltage potential as the output signal and a source at the same voltage potential as the second supply voltage.

8. The voltage selection circuit of claim 7 , further comprising disabling the second device by forcing a gate node of the second device to a value of the first supply voltage.

9. The voltage selection circuit of claim 7 , further comprising disabling the first device by forcing a gate node of the first device to a value of the second supply voltage.

10. A circuit comprising:

a p-channel field effect transistor circuit comprising a first device and a second device such that the p-channel field effect transistor circuit is configured to output a higher voltage of a first supply voltage and a second supply voltage through one of the first device and the second device, wherein the first device and the second device are connected to output an output signal; and

a gate control circuit comprising

a third device comprising

an NWELL at a same voltage potential as the output signal,

a source at a same voltage potential as the second supply voltage, and

a drain at the same voltage potential as a gate of a fourth device, and

the fourth device comprising

an NWELL at the same voltage potential as the output signal,

a source at the same voltage potential as the first supply voltage, and

a drain at the same voltage potential as the gate of the third device, and

a voltage difference between the first supply voltage and the second supply voltage is less than a threshold voltage.

11. The circuit of claim 10 , wherein:

the first device is a PMOS; and

the PMOS transistor comprises a source at the same voltage potential as the first supply voltage.

12. The circuit of claim 11 , wherein:

the second device is a PMOS transistor; and

the PMOS transistor comprises a source at the same voltage potential as the second supply voltage.

13. The circuit of claim 11 , wherein each of the first device and the second device includes a drain at the same voltage potential as the output signal.

14. The circuit of claim 12 , further comprising a gate bias circuit, wherein:

the gate bias circuit comprises a fifth device and a sixth device;

the fifth device comprises

an NWELL at the same voltage potential as the output signal, and

a source at the same voltage potential as the first supply voltage; and

the sixth device comprises

an NWELL at the same voltage potential as the output signal, and

a source at the same voltage potential as the second supply voltage.

15. The circuit of claim 10 , further comprising disabling the second device by forcing a gate node of the second device to a value of the first supply voltage.

16. The circuit of claim 10 , further comprising disabling the first device by forcing a gate node of the first device to a value of the second supply voltage.

17. The circuit of claim 10 , further comprising a standby control circuit comprising a level translator, a NOR gate, a buffer, and an inverter.

18. A method, comprising:

generating a bias voltage in response to a voltage difference between a first supply voltage and a second supply voltage being less than a threshold voltage;

outputting via a first device and a second device of a voltage selection circuit an output signal to a higher voltage of the first supply voltage and the second supply voltage in response to the generated bias voltage; and

providing the output signal to an NWELL of a third device of the voltage selection circuit.

19. The method of claim 18 , further comprising disabling the second device by forcing a gate node of the second device to a value of the first supply voltage.

20. The method of claim 18 , further comprising disabling the first device by forcing a gate node of the first device to a value of the second supply voltage.

21. The method of claim 18 , further comprising:

supplying the first supply voltage or the second supply voltage to a source of the third device; and

supplying the first supply voltage or the second supply voltage to a gate of the third device.