Apparatuses and methods for parallel writing to multiple memory device structures
The present disclosure includes apparatuses and methods related to a memory device as the store to pre-resolved instructions. An example apparatus comprises a memory device coupled to a host via a data bus and a control bus. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes sense amplifiers and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of address translated instructions and/or constant data from the host. The memory controller is configured to write the address translated instructions and/or constant data to a plurality of locations in a bank of the memory device in parallel.
1. An apparatus, comprising:
a memory device, wherein the memory device comprises:
an array of memory cells;
sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations; and
a memory controller coupled to the array and sensing circuitry, the memory controller configured to:
receive a block of resolved instructions and/or constant data to a plurality of locations in a bank of a plurality of banks via a bank arbiter;
set a series of registers in the bank arbiter to mask bank address bits and row address bits for the plurality of locations in the plurality of banks; and
dispatch the resolved instructions and/or constant data to the bank associated with the memory controller in order to write to a plurality of locations in the bank in parallel; and
write the resolved instructions and/or constant data to a plurality of locations in parallel.
2. The apparatus of claim 1 , where the memory controller is configured to:
receive the resolved instructions and/or constant data to set up processor-in-memory (PIM) calculations from the host; and
write the resolved instructions and/or constant data to a plurality of locations in a bank of the memory device in parallel.
3. The apparatus of claim 1 , wherein the array of memory cells are dynamic random access memory (DRAM) cells.
4. The apparatus of claim 1 , wherein the resolved instructions and/or constant data include processor-in-memory (PIM) commands.
5. An apparatus, comprising:
a memory device, wherein the memory device comprises:
an array of memory cells;
sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations; and
a memory controller coupled to the array and sensing circuitry, the memory controller configured to:
read a series of registers set on the memory controller to send resolved instructions and/or constant data to a plurality of subarrays in a bank associated with the memory controller;
write the resolved instructions and/or constant data to a plurality of locations in the bank of the memory device in parallel;
receive a multicast command via bank arbiters addressed to the bank in a plurality of banks among the plurality of memory devices, from the memory controller; and
use the addressed bank arbiters to set the series of registers for the plurality of banks to be included in a multicast write operation.
6. The apparatus of claim 5 , wherein the plurality of locations are a plurality of subarrays in each of the plurality of banks.
7. The apparatus of claim 6 , wherein the plurality of subarrays are different among select ones of the plurality of banks.
8. The apparatus of claim 5 , wherein the memory controller is configured to dispatch the multicast command to select ones of the plurality of memory devices.
9. The apparatus of claim 8 , wherein the addressed bank arbiters are configured to dispatch the resolved instructions and/or constant data to select ones of the plurality of banks.
10. The apparatus of claim 5 , wherein the memory controller is configured to control the sensing circuitry to perform non-Boolean logic operations including copy, compare and erase.
11. The apparatus of claim 5 , wherein the bank arbiter is configured to set the series of registers to mask bank address and row address bits for the plurality of banks in a multicast data write operation.
12. A method for operating a memory device to parallel write to a plurality of locations, comprising:
receiving resolved instructions and/or constant data to a plurality of locations in a bank of a plurality of banks in the memory device via a bank arbiter, wherein the bank comprises:
an array of memory cells;
sensing circuitry coupled to the array via a plurality of sense lines, the sensing circuitry including sense amplifiers and a compute component configured to implement logical operations; and
a memory controller coupled to the array and the sensing circuitry;
setting a series of registers in the bank arbiter to mask bank address bits and row address bits for the plurality of locations in the plurality of banks;
receiving a multicast write command to the bank;
performing the multicast data write operation in parallel to the plurality of locations in the bank; and
dispatching the resolved instructions to the bank in order to write to the plurality of locations in the bank in parallel.
13. The method of claim 12 , wherein the method comprises:
receiving resolved instructions and/or constant data to the bank of a dynamic random access memory array (DRAM); and
performing the multicast data write operation to a plurality of subarrays to the DRAM.
14. The method of claim 12 , wherein the method comprises receiving an augmented DRAM write command to a bank arbiter coupled to the memory controller to indicate when writes are to be performed in a multicast manner.
15. The method of claim 12 , wherein the method comprises performing the multicast data write operation using a DRAM write path.
16. The method of claim 12 , wherein the method comprises:
setting the series of registers to mask odd numbered subarrays address in even numbered banks; and
setting the series of registers to mask even numbered subarrays in odd numbered banks.
17. The method of claim 12 , wherein the method comprises:
receiving the multicast write command to the bank arbiter in a plurality of memory devices from a channel controller, wherein the resolved instructions and/or constant data are pre-resolved by the channel controller;
reading the series of registers set in each of the bank arbiters;
performing the multicast data write operation in parallel to resolved locations in the plurality of banks in the plurality of memory devices and to resolved locations in a plurality of subarrays in respective banks using a dynamic random access memory (DRAM) write path.
18. The method of claim 17 , wherein the resolved locations for the plurality of subarrays is different between the resolved locations of the plurality of banks.