Scan driver and display device for driving a plurality of scan lines
A scan driver includes a plurality of circuit stages, each circuit stage including a first input part configured to transfer a carry signal to a first node in response to a first clock signal, a second input part configured to transfer the first clock signal to a second node in response to a signal of the first node, a first output part configured to transfer a third clock signal to an output terminal in response to a signal of the second node, a holding part configured to maintain a signal of a third node response to a second clock signal, and a second output part configured to transfer a signal of the third node to the output terminal in response to the second clock signal.
1. A scan driver comprising a plurality of circuit stages cascade-connected with each other and outputting a plurality of gate signals, each of the plurality of circuit stages comprising:
a first input part configured to transfer a carry signal to a first node in response to a first clock signal;
a second input part configured to transfer the first clock signal to a second node in response to a signal of the first node;
a first output part configured to transfer a third clock signal to an output terminal in response to a signal of the second node;
a holding part configured to maintain a signal of a third node in response to a second clock signal;
a second output part configured to transfer a signal of the third node to the output terminal in response to the second clock signal:
a first output control part configured to transfer the first clock signal to the second node in response to the first clock signal; and
a second output control part configured to transfer a signal of the first node to the third node in response to a first driving voltage,
wherein the second output control part comprises:
an eighth transistor including a control electrode connected to a first driving voltage terminal and receiving always constant voltage that is the first driving voltage, a first electrode connected to the first node, and a second electrode connected to the third node.
2. The scan driver of claim 1 , wherein the holding part comprises a sixth transistor and a seventh transistor,
the sixth transistor comprises a control electrode connected to the second node, a first electrode connected to the seventh transistor and a second electrode connected to the output terminal, and
the seventh transistor comprises a control electrode receiving the second clock signal, a first electrode connected to the third node and a second electrode connected to the sixth transistor.
3. The scan driver of claim 1 , further comprising a simultaneous driving part configured to control the second output part in response to the third clock signal,
wherein the third clock signal has a first level for a simultaneous driving period and a second level for a sequential driving period, and
the simultaneous driving part is configured to apply a second level of a second driving voltage to the third node in response to the first level of the third clock signal in the simultaneous driving period.
4. The scan driver of claim 3 , wherein the simultaneous driving part comprises a ninth transistor,
the ninth transistor comprises a control electrode connected to a third clock terminal, a first electrode connected to a second driving voltage terminal and a second electrode connected to the first node.
5. The scan driver of claim 3 , wherein the simultaneous driving part comprises a ninth transistor,
the ninth transistor comprises a control electrode connected to a third clock terminal, a first electrode connected to a second driving voltage terminal and a second electrode connected to the third node.
6. The scan driver of claim 1 , wherein the first output part comprises a first transistor and a first capacitor,
the first transistor comprises a control electrode connected to the second node, a first electrode connected to a third clock terminal and a second electrode connected to the output terminal, and
the first capacitor comprises a first electrode connected to the third clock terminal and a second electrode connected to the second node.
7. The scan driver of claim 1 , wherein the second output part comprises a second transistor and a second capacitor,
the second transistor comprises a control electrode connected to the third node, a first electrode connected to a second clock terminal and a second electrode connected to the output terminal, and
the second capacitor comprises a first electrode connected to the output terminal and a second electrode connected to the third node.
8. The scan driver of claim 1 , further comprising:
a selecting part configured to output a previous scan signal outputted from a previous circuit stage of the plurality of circuit stages or a next scan signal outputted from a next circuit stage of the plurality of circuit stages to the first input part in response to a first direction signal and a second direction signal.
9. A display device comprising:
a display panel comprising a switching transistor connected to a scan line and a data line, an emission control transistor connected to the switching transistor and an organic light emitting diode;
a timing controller configured to generate a first clock signal, a second clock signal different from the first clock signal and a third clock signal different from the first clock signal and the second clock signal;
a scan driver configured to generate a plurality of scan signals based on the first clock signal, the second clock signal, and the third clock signal, to simultaneously output the plurality of scan signals during a simultaneous driving period and to sequentially output the plurality of scan signals during a sequential driving period, the scan driver comprises a plurality of circuit stages cascade-connected with each other, each circuit stage of the plurality of circuit stages comprising:
a first input part configured to transfer a carry signal to a first node in response to a first clock signal;
a second input part configured to transfer the first clock signal to a second node in response to a signal of the first node;
a first output part configured to transfer a third clock signal to an output terminal in response to a signal of the second node;
a holding part configured to maintain a signal of a third node in response to a second clock signal;
a second output part configured to transfer a signal of the third node to the output terminal in response to the second clock signal:
a first output control part configured to transfer the first clock signal to the second node in response to the first clock signal; and
a second output control part configured to transfer a signal of the first node to the third node in response to a first driving voltage,
wherein the second output control part comprises:
an eighth transistor including a control electrode connected to a first driving voltage terminal and receiving always constant voltage that is the first driving voltage, a first electrode connected to the first node, and a second electrode connected to the third node.
10. The display device of claim 9 , wherein the holding part comprises a sixth transistor and a seventh transistor,
the sixth transistor comprises a control electrode connected to the second node, a first electrode connected to the seventh transistor and a second electrode connected to the output terminal, and
the seventh transistor comprises a control electrode receiving the second clock signal, a first electrode connected to the third node and a second electrode connected to the sixth transistor.
11. The display device of claim 9 , wherein each circuit stage of the plurality of circuit stages further comprises a simultaneous driving part configured to turn off the second output part in response to the third clock signal,
wherein the third clock signal has a first level for a simultaneous driving period and a second level for a sequential driving period, and
the simultaneous driving part configured to apply a second level of a second driving voltage to the third node in response to the first level of the third clock signal in the simultaneous driving period.
12. The display device of claim 11 , wherein the simultaneous driving part comprises a ninth transistor,
the ninth transistor comprises a control electrode connected to a third clock terminal, a first electrode connected to a second driving voltage terminal, and a second electrode connected to the first node.
13. The display device of claim 11 , wherein the simultaneous driving part comprises a ninth transistor,
the ninth transistor comprises a control electrode connected to the third clock terminal, a first electrode connected to a second driving voltage terminal and a second electrode connected to the third node.
14. The display device of claim 9 , wherein the first output part comprises a first transistor and a first capacitor,
the first transistor comprises a control electrode connected to the second node, a first electrode connected to a third clock terminal and a second electrode connected to the output terminal, and
the first capacitor comprises a first electrode connected to the third clock terminal and a second electrode connected to the second node.
15. The display device of claim 9 , wherein the second output part comprises a second transistor and a second capacitor,
the second transistor comprises a control electrode connected to the third node, a first electrode connected to a second clock terminal and a second electrode connected to the output terminal, and
the second capacitor comprises a first electrode connected to the output terminal and a second electrode connected to the third node.
16. The display device of claim 9 , wherein the timing controller is configured to output a first direction signal corresponding to a forward direction scan direction and a second direction signal corresponding to a reverse direction scan direction to the scan driver, and
each circuit stage of the plurality of circuit stages further comprises a selecting part configured to output a previous scan signal outputted from a previous circuit stage of the plurality of circuit stages or a next scan signal outputted from a next circuit stage of the plurality of circuit stages to the first input part in response to a first direction signal and a second direction signal.