IP Library › Granted Patent US 10,586,849
Granted Patent B2
US 10,586,849 · App. 16/434,711 · Granted Mar 10, 2020

Field effect transistor with controllable resistance

Inventors: Yulong Li (Westchester, NY); Paul M. Solomon (Westchester, NY); Siyuranga Koswatta (Carmel, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/1045H01L27/10805H01L27/1159H01L27/11521H01L27/24H01L29/0646H01L29/1054H01L29/165H01L29/205H01L29/40111H01L29/40114H01L29/42324H01L29/4983H01L29/516H01L29/66431H01L29/66659H01L29/66977H01L29/685H01L29/785H01L29/7881H01L29/802H01L29/6684H01L29/66825H01L29/788H01L29/78391
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,586,849
App. No.
16/434,711
Granted
Mar 10, 2020
Kind
B2
Abstract

A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

Claims (16)

1. A method for forming a semiconductor device, the method comprising:

forming a source terminal of a semiconductor fin on a substrate;

forming an energy barrier on a surface of the source terminal;

forming a channel on a surface of the energy barrier;

forming a drain terminal on a surface of the channel;

recessing the drain terminal and the channel on either sides of the channel;

etching the energy barrier in recesses formed by the recessing;

recessing the source terminal using timed etching to remove a portion of the source terminal in recesses formed by etching the energy barrier;

forming a first bottom spacer on a surface of the source terminal and a sidewall of the semiconductor fin; and

forming a gate stack on a surface of the first bottom spacer.

2. The method of claim 1 further comprising:

etching the gate stack;

forming a second bottom spacer on a surface of the gate stack;

forming an active contact connecting the drain terminal with a first line; and

forming a gate contact connecting the gate stack with a second line.

3. The method of claim 1 , wherein the first bottom spacer is composed of a silicon nitride, the drain terminal and the source terminal are composed of P+ doped SiGe, and the channel is composed of N− doped SiGe, and the energy barrier is composed of Si.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2019
From: LI, YULONG; SOLOMON, PAUL M.; KOSWATTA, SIYURANGA
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 049406/0407 →
Continuity (2)
Continuation 15850098 · Dec 21, 2017
Related Publication 20190312108A1 · Oct 10, 2019