Vertical thin film transistor structures with localized gate dielectric
Transistor structures with a deposited channel semiconductor material may have a vertical structure that includes a gate dielectric material that is localized to a sidewall of a gate electrode material layer. With localized gate dielectric material threshold voltage variation across a plurality of vertical transistor structures, such as a NAND flash memory string, may be reduced. A via may be formed through a material stack, exposing a sidewall of the gate electrode material layer and sidewalls of the dielectric material layers. A sidewall of the gate electrode material layer may be recessed selectively from the sidewalls of the dielectric material layers. A gate dielectric material, such as a ferroelectric material, may be selectively deposited upon the recessed gate electrode material layer, for example at least partially backfilling the recess. A semiconductor material may be deposited on sidewalls of the dielectric material layers and on the localized gate dielectric material.
1. A vertical transistor structure, comprising:
a material layer stack comprising a first dielectric material layer, a second dielectric material layer, and a gate electrode material layer therebetween;
a semiconductor material in direct contact with a sidewall of both the first and second dielectric material layers, wherein the semiconductor material is within a via extending through the material layer stack, the via having a lower diameter associated with the sidewall of the first dielectric material layer, and an upper diameter associated with the sidewall of the second dielectric material layer, and wherein a thickness of the semiconductor material, in a direction normal to the sidewall of the second dielectric material, is less than half of the upper diameter;
a gate dielectric material between the semiconductor material and a sidewall of the gate electrode material layer, wherein the gate dielectric material has a higher relative permittivity than the first and second dielectric material layers; and
first and second terminal contacts coupled to the semiconductor material on opposite sides of the gate electrode, wherein:
a sidewall of the gate electrode material layer is recessed laterally from the sidewall of both the first and second dielectric material layers;
the semiconductor material is in contact with the gate dielectric material;
the gate dielectric material is between the first and second dielectric materials; and
a thickness of the gate dielectric material is no greater than an amount by which the sidewall of the gate electrode material layer is recessed laterally from the sidewall of the second dielectric material layer.
2. The vertical transistor structure of claim 1 , wherein:
the gate electrode material layer comprises a metal.
3. The vertical transistor structure of claim 1 , wherein the gate dielectric material comprises a ferroelectric material.
4. The vertical transistor structure of claim 3 , wherein the gate dielectric material comprises O and at least one of Hf, Al, Zn, or Zr.
5. The vertical transistor structure of claim 1 , wherein an interface between the gate dielectric and the semiconductor material is within 5 nm of the sidewall of both the first and second dielectric material layers.
6. The vertical transistor structure of claim 1 , wherein:
the semiconductor material is within a via extending through the material layer stack, the via having an upper diameter defined by the sidewall of the second dielectric material layer, and a lower diameter defined by the sidewall of the first dielectric material layer;
the gate dielectric material is a cylindrical structure that surrounds a channel portion of the semiconductor material, the cylindrical structure having an outer diameter that is larger than at least one of the upper and lower diameters; and
the gate electrode material layer surrounds the cylindrical structure.
7. The vertical transistor structure of claim 6 , wherein the cylindrical structure has an inner diameter that is at least as large as the lower diameter of the via.
8. The vertical transistor structure of claim 6 , wherein the gate dielectric material is in direct contact with a sidewall of each of the gate electrode material layers, and the semiconductor material is in direct contact with the gate dielectric material.
9. The vertical transistor structure of claim 6 , wherein:
the semiconductor material is within a via extending through the material layer stack, the via having an upper diameter associated with the sidewall of the second dielectric material layer, and a lower diameter associated with the sidewall of the first dielectric material layer;
each of the cylindrical structures surrounds a channel portion of the semiconductor material, each of the cylindrical structures having an outer diameter that is larger than at least one of the upper and lower diameters; and
each of the gate electrode material layers surrounds one of the cylindrical structures.
10. The vertical transistor structure of claim 9 , wherein:
the upper diameter is no more than 50 nm;
the outer diameter of the cylindrical structure is not more than 15 nm greater than an inner diameter of the cylindrical structure; and
the semiconductor material has a thickness of at least 5 nm.
11. The vertical transistor structure of claim 1 , wherein:
the material stack further comprises a plurality of gate electrode material layers, each gate electrode material layer separated from another by a dielectric material layer;
the semiconductor material is in direct contact with a sidewall of each of the dielectric material layers;
a plurality of cylindrical structures comprises the gate dielectric material, each of the cylindrical structures being between the semiconductor material and a sidewall of one of the gate electrode material layers; and
the plurality of gate electrode material layers are between the first and second terminal contacts.
12. An integrated circuit (IC) die, comprising:
a plurality of complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) structures, wherein individual ones of the CMOS FET structures comprise a Group IV semiconductor material;
a plurality of back-end transistor structures over the CMOS FET structures, with one or more levels of interconnect metallization therebetween, wherein individual ones of the back-end transistor structures comprise the vertical transistor structure of claim 1 .
13. The vertical transistor structure of claim 1 , further comprising a dielectric material within the via, wherein the semiconductor material is a cylindrical structure and the dielectric material within the via is surrounded by the semiconductor material.
14. A vertical Fe-NAND memory structure, comprising:
a material stack comprising a plurality of gate electrode material layers, each gate electrode material layer separated from another by a dielectric material layer;
a via extending through the material layer stack, the via having a lower diameter defined by a sidewall of a first dielectric material layer, an upper diameter defined by a sidewall of a second dielectric material layer, and a plurality of expanded diameters, wherein each of the expanded diameters is defined by a sidewall of one the gate electrode material layers, and the expanded diameter is larger than at least one of the lower and upper diameters;
a plurality of cylindrical structures, each comprising a ferroelectric gate dielectric material, wherein an outer sidewall of individual ones of the cylindrical structures is in direct contact with a sidewall of individual ones of the gate electrode material layers, and wherein an inner diameter of individual ones of the cylindrical structures is no smaller than the lower diameter; and
a semiconductor material within the via in direct contact with the sidewalls of the first and second dielectric material layers, and in direct contact with an inner sidewall of individual ones of the cylindrical structure, wherein a thickness of the semiconductor material, in a direction normal from the sidewall of the second dielectric material, is less than half of the upper diameter.
15. The vertical Fe-NAND memory structure of claim 14 , wherein the plurality of gate electrode material layers are coupled to wordlines.
16. The vertical Fe-NAND memory structure of claim 15 , wherein the gate dielectric material comprises O and at least one of Hf, Al, Zn, or Zr.
17. The vertical Fe-NAND memory structure of claim 14 , further comprising a dielectric material within the via, wherein the semiconductor material is a cylindrical structure and the dielectric material within the via is surrounded by the semiconductor material.