Systems and methods for reducing standby power in floating body memory devices
Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
1. A system for reducing standby power, said system comprising:
a memory array comprising a plurality of floating body memory cells each comprising a floating body configured to store charge representative of data, wherein said charge is maintained by a vertical bipolar holding mechanism;
a reference cell configured to measure a potential level of said floating body;
a high level floating body potential detector and a low level floating body potential detector; and
a controller configured to turn on or turn off said vertical bipolar holding mechanism based on comparison between said potential level measured by said reference cell and said high level floating body potential detector and said low level floating body potential detector.
2. The system of claim 1 , further comprising:
a voltage regulator;
wherein when the low level floating body potential detector inputs a signal to the controller indicating that a predetermined low potential has been measured, said controller controls said voltage regulator to lower a voltage level input to a source line connected to said floating body memory cell or a bit line connected to said floating body memory cell to turn on the vertical bipolar holding mechanism; and
wherein when the high level floating body potential detector inputs a signal to the controller indicating that a predetermined high potential has been measured, said controller controls said voltage regulator to increase the voltage level input to said source line or said bit line to turn off the vertical bipolar holding mechanism.
3. The system of claim 1 , further comprising:
a DNWell line connected to said floating body memory cell;
wherein when the low level floating body potential detector inputs a signal to the controller indicating that a predetermined low potential has been measured, said controller controls said voltage regulator to increase a voltage level input to the DNWell line to turn on the vertical bipolar holding mechanism; and
wherein when the high level floating body potential detector inputs a signal to the controller indicating that a predetermined high potential has been measured, said controller controls said voltage regulator to lower the voltage level input to the DNWell line to turn off the vertical bipolar holding mechanism.
4. The system of claim 1 , further comprising:
source lines, bit lines and DNWell lines respectively connected to said floating body memory cells; and
a plurality of equalization transistors connected to said source lines, bit lines and DNWell lines;
wherein said equalization transistors are configured to be turned on to equalize charge among said source lines or bit lines or DNWell lines and to be subsequently turned off prior to said controller turning off or turning on said vertical bipolar holding mechanism.
5. A system for reducing standby power, said system comprising:
a floating body memory cell having at least two stable floating body charge levels, wherein the standby power of one of said at least two stable floating body charge levels is lower than the other of said at least two stable floating body charge levels; and
a controller configured to temporarily disable a vertical bipolar holding mechanism of said floating body memory cell.
6. The system of claim 5 , wherein said floating body memory cell further comprises a floating body region having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type.
7. The system of claim 6 , wherein said floating body memory cell further comprises a back-bias region having a second conductivity type selected from a p-type conductivity type and an n-type conductivity type, wherein said second conductivity type is different from said first conductivity type.
8. The system of claim 7 , wherein applying a back-bias to said back-bias region results in maintenance of said floating body charge levels.
9. The system of claim 8 , wherein said back bias applied to said back-bias region is a constant positive voltage bias.
10. The system of claim 8 , wherein said back bias applied to said back-bias region is a periodic pulse of positive voltage.
11. The system of claim 5 , wherein said controller is configured to identify whether at least one of said stable charge levels remains currently needed for storage of data by said floating body memory cell.
12. The system of claim 5 , wherein said controller is configured to identify when said floating body memory cell stores data that is not being actively used.
13. The system of claim 5 , wherein said controller is configured to identify when said floating body memory cell does not store any valid data.