IP Library Granted Patent US 11,735,533
Granted Patent B2
US 11,735,533 · App. 16/437,254 · Granted Aug 22, 2023

Heterogeneous nested interposer package for IC chips

Inventors: Debendra Mallik (Chandler, AZ); Ravindranath Mahajan (Chandler, AZ); Robert Sankman (Phoenix, AZ); Shawna Liff (Scottsdale, AZ); Srinivas Pietambaram (Chandler, AZ); Bharat Penmecha (Phoenix, AZ)
Assignee: Intel Corporation
H01L23/562H01L21/486H01L21/4853H01L21/4857H01L21/565H01L21/568H01L23/3128H01L23/5381H01L23/5384H01L23/5385H01L23/5386H01L24/16H01L2224/16227H01L2924/3511
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Quick Facts
Patent No.
US 11,735,533
App. No.
16/437,254
Granted
Aug 22, 2023
Kind
B2
Abstract

Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

Claims (42)

1. An electronic package, comprising:

an interposer, wherein a cavity passes through the interposer;

a nested component in the cavity; and

a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect, wherein the first and second interconnects comprise:

a first bump;

a bump pad over the first bump; and

a second bump over the bump pad.

2. The electronic package of claim 1 , wherein the bump pad of the first interconnect is substantially coplanar to the bump pad of the second interconnect.

3. The electronic package of claim 1 , wherein the nested component and the interposer are embedded in an underfill layer and a first mold layer.

4. The electronic package of claim 3 , wherein the die is embedded in a second mold layer.

5. The electronic package of claim 1 , wherein the cavity is entirely within a footprint of the die.

6. The electronic package of claim 1 , wherein a first portion of the cavity is within a footprint of the die, and wherein a second portion of the cavity is outside of the footprint of the die.

7. The electronic package of claim 1 , wherein through component vias extend through the nested component.

8. The electronic package of claim 1 , wherein the nested component is a passive component.

9. The electronic package of claim 1 , wherein the nested component is an active component.

10. The electronic package of claim 1 , further comprising:

a second die, wherein the second die is coupled to the nested component by a third interconnect comprising:

a first bump;

a bump pad over the first bump; and

a second bump over the bump pad.

11. The electronic package of claim 10 , wherein the nested component electrically couples the first die to the second die.

12. The electronic package of claim 1 , further comprising:

a second nested component in the cavity.

13. The electronic package of claim 1 , wherein an active surface of the nested component faces away from the die.

14. The electronic package of claim 1 , wherein the nested component comprises a plurality of stacked dies.

15. The electronic package of claim 1 , wherein the interposer comprises a plurality of discrete interposer substrates, wherein edges of the plurality of discrete interposer substrates define the cavity.

16. The electronic package of claim 1 , wherein the interposer comprises glass, ceramic, silicon, or organic materials.

17. The electronic package of claim 1 , further comprising one or more redistribution layers, wherein the one or more redistribution layers are located over a top surface of the interposer, over a bottom surface of the interposer, over a top surface of the nested component, over a bottom surface of the nested component, over a mold layer that embeds the interposer and the nested component, and/or between the first bumps and the second bumps.

18. An electronic system, comprising:

a board;

a package substrate electrically coupled to the board;

an interposer electrically coupled to the package substrate, wherein the interposer comprises a cavity;

a nested component in the cavity, wherein the nested component is electrically coupled to the package substrate;

a first die electrically coupled to the interposer and the nested component by first interconnects; and

a second die electrically coupled to the interposer and the nested component by second interconnects, wherein each of the first interconnects and each of the second interconnects:

a first bump;

a bump pad over the first bump; and

a second bump over the bump pad.

19. The electronic system of claim 18 , wherein the nested component electrically couples the first die to the second die.

20. The electronic system of claim 18 , wherein the nested component is a passive component.

21. The electronic system of claim 18 , wherein the nested component is an active component.

22. The electronic system of claim 18 , wherein the nested component comprises a plurality of stacked dies.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2019
From: MALLIK, DEBENDRA; MAHAJAN, RAVINDRANATH; SANKMAN, ROBERT; LIFF, SHAWNA; PIETAMBARAM, SRINIVAS; PENMECHA, BHARAT
To: INTEL CORPORATION
Reel/Frame 051085/0172 →
Continuity (1)
Related Publication 20200395313A1 · Dec 17, 2020