Parasitic voltage drop compensation in large cross-point arrays

1. A cross-point array, comprising:

an array of Resistive Processing Unit (RPU) devices having rows and columns interconnected at cross-points; and

a plurality of series resistors, each respective one of the plurality of series resistors having a first end connected in series with a respective one of the RPU devices and a second end connected to a respective one of the cross-points to compensate for a parasitic voltage drop associated with each of the RPU devices,

wherein a particular one of the plurality of series resistors connected to a particular one of the RPU devices having a highest voltage drop from among the RPU devices is assigned a resistance value of zero, and wherein another one of the plurality of series resistors connected to another one of the RPU devices having a lowest voltage drop from among the RPU devices is assigned a highest resistor value from a list of potential values determining using interpolation.

2. The cross-point array of claim 1 , wherein a respective value of each of the plurality of series resistors is selected so as to produce a same voltage drop between the cross-points of the array.

3. The cross-point array of claim 1 , wherein a respective value of each given resistor from among the plurality of series resistors is selected based on a worst-case voltage drop expected at the corresponding one of the cross-points to which the given resistor is connected.

4. The cross-point array of claim 1 , wherein a respective value of each given resistor from among the plurality of series resistors is selected based on a minimum possible resistance of the respective one of the RPU devices to which the given resistor is connected.

5. The cross-point array of claim 1 , wherein a respective value of each given resistor from among the plurality of series resistors is selected using a diagonal symmetry approach that assigns a same resistance value to respective ones of the plurality of series resistors situated along a same diagonal line taken across the cross-point array.

6. The cross-point array of claim 1 , wherein a resistance of each of the plurality of series resistors is set using a control type selected from the group consisting of an area-type resistance control, a width-type resistance control, and a length-type resistance control.

7. The cross-point array of claim 1 , wherein a resistance of each of the plurality of series resistors is set using an oxide.

8. The cross-point array of claim 1 , wherein a resistance of each of the plurality of series resistors is set using dimension control on a set of resistive vias.

9. The cross-point array of claim 1 , wherein the plurality of series resistors are implemented by active elements, wherein a gate voltage control operation is performed on the active elements to adjust a resistance of each of the active elements.

10. The cross-point array of claim 9 , wherein the active elements comprise field effect transistors.

11. The cross-point array of claim 1 , wherein values for the plurality of series resistors are selected under a constraint that the values decrement for each subsequent one of the plurality of series resistors in a given row and a given column with respect to a voltage source.

12. A method of forming a cross-point array, comprising:

forming an array of Resistive Processing Unit (RPU) devices having rows and columns interconnected at cross-points; and

forming a plurality of series resistors, each respective one of the plurality of series resistors having a first end connected in series with a respective one of the RPU devices and a second end connected to a respective one of the cross-points to compensate for a parasitic voltage drop associated with each of the RPU devices,

wherein a particular one of the plurality of series resistors connected to a particular one of the RPU devices having a highest voltage drop from among the RPU devices is assigned a resistance value of zero, and wherein another one of the plurality of series resistors connected to another one of the RPU devices having a lowest voltage drop from among the RPU devices is assigned a highest resistor value from a list of potential values determining using interpolation.

13. The cross-point array of claim 12 , further comprising selecting a respective value of each of the plurality of series resistors so as to produce a same voltage drop between the cross-points of the array.

14. The cross-point array of claim 12 , further comprising selecting a respective value of each given resistor from among the plurality of series resistors based on a worst-case voltage drop expected at the corresponding one of the cross-points to which the given resistor is connected.

15. The cross-point array of claim 12 , further comprising selecting a respective value of each given resistor from among the plurality of series resistors based on a minimum possible resistance of the respective one of the RPU devices to which the given resistor is connected.

16. The cross-point array of claim 12 , further comprising selecting a respective value of each given resistor from among the plurality of series resistors using a diagonal symmetry approach that assigns a same resistance value to respective ones of the plurality of series resistors situated along a same diagonal line taken across the cross-point array.

17. The cross-point array of claim 12 , further comprising setting a resistance of each of the plurality of series resistors using a control type selected from the group consisting of an area-type resistance control, a width-type resistance control, and a length-type resistance control.

18. The cross-point array of claim 12 , further comprising setting a resistance of each of the plurality of series resistors using an oxide.

19. The cross-point array of claim 12 , further comprising setting a resistance of each of the plurality of series resistors using dimension control on a set of resistive vias.