High density IC capacitor structure
High density integrated circuit (IC) capacitor structures and fabrication methods that increase the capacitive density of integrated capacitors with little or no reduction in Q-factor by using a stacked high-density integrated capacitor structure that includes substrate-contact (“S-contact”) capacitor plates. Embodiments include a plurality of S-contact plates fabricated in electrical connection with a capacitor formed in a metal interconnect layer. Some embodiments include interstitial S-contact plates to provide additional capacitive density. Embodiments may also utilize single-layer transfer (SLT) and double-layer transfer (DLT) techniques to create ICs with high density, high Q-factor capacitors. Such capacitors can be beneficially combined with other structures made possible in SLT and DLT IC structures, such as metal interconnect layer capacitors and inductors, and one or more FETs having a conductive aligned supplemental gate. Embodiments are compatible with fabrication of CMOS SOI transistors, and are particularly suitable for radio frequency and analog applications.
1. An integrated circuit including at least one integrated capacitor structure including (a) at least one capacitor formed from a portion of at least one metal interconnect layer, and (b) a plurality of substrate-contact (S-contact) plates formed in electrical contact with at least one capacitor and configured to increase the capacitive density of the at least one capacitor.
2. The invention of claim 1 , the integrated circuit further including a fabrication region proximate the at least one metal interconnect layer, a BOX layer proximate the fabrication region, and a substrate proximate the BOX layer, wherein the S-contact plates penetrate through the fabrication region and the BOX layer to the substrate.
3. The invention of claim 1 , the integrated circuit further including a fabrication region proximate the at least one metal interconnect layer, a BOX layer proximate the fabrication region, and a substrate proximate the BOX layer, wherein the S-contact plates penetrate through the fabrication region and partially penetrate the BOX layer.
4. The invention of claim 1 , wherein at least one capacitor includes first and second lateral interdigitated structures.
5. The invention of claim 1 , wherein at least one integrated capacitor structure includes a plurality of stacked lateral capacitors each comprising first and second interdigitated structures.
6. The invention of claim 1 , wherein at least one capacitor includes first and second lateral interdigitated structures each having at least one finger, each finger aligned with and in electrical contract with a corresponding one of the plurality of S-contact plates.
7. The invention of claim 1 , wherein at least one capacitor includes first and second lateral interdigitated structures each having at least one finger, each finger aligned with and in electrical contract with a corresponding one of the plurality of S-contact plates, and further including at least one interstitial S-contact plate positioned between adjacent fingers.
8. The invention of claim 1 , wherein the integrated circuit further includes at least one field effect transistor.
9. The invention of claim 1 , wherein the integrated circuit further includes at least one field effect transistor having a conductive aligned supplemental gate.
10. The invention of claim 1 , wherein the integrated circuit further includes a redistribution layer and at least one additional capacitor and/or inductor formed from a portion of the at least one metal interconnect layer and a portion of the redistribution layer.
11. The invention of claim 1 , wherein the integrated circuit further includes at least one inductor formed from a portion of the at least one metal interconnect layer.
12. An integrated circuit including a substrate, a buried-oxide (BOX) layer formed proximate the substrate, a fabrication region formed proximate the BOX layer, a region of interlayer dielectric formed proximate the BOX layer, at least one metal interconnect layer formed proximate the region of interlayer dielectric, and at least one integrated lateral capacitor structure including (a) at least one capacitor formed from a portion of at least one of the at least one metal interconnect layer, and (b) a plurality of substrate-contact (S-contact) plates formed in electrical contact with at least one of the at least one capacitor and configured to increase the capacitive density of the at least one of the at least one capacitor.
13. The invention of claim 12 , wherein the S-contact plates penetrate through the fabrication region and the BOX layer to the substrate.
14. The invention of claim 12 , wherein the S-contact plates penetrate through the fabrication region and partially penetrate the BOX layer.
15. The invention of claim 12 , wherein at least one capacitor includes first and second lateral interdigitated structures.
16. The invention of claim 12 , wherein at least one integrated lateral capacitor structure includes a plurality of stacked lateral capacitors each comprising first and second interdigitated structures.
17. The invention of claim 12 , wherein at least one capacitor includes first and second lateral interdigitated structures each having at least one finger, each finger aligned with and in electrical contract with a corresponding one of the plurality of S-contact plates.
18. The invention of claim 12 , wherein at least one capacitor includes first and second lateral interdigitated structures each having at least one finger, each finger aligned with and in electrical contract with a corresponding one of the plurality of S-contact plates, and further including at least one interstitial S-contact plate positioned between adjacent fingers.
19. The invention of claim 12 , wherein the integrated circuit further includes at least one field effect transistor formed on and/or in the fabrication region.
20. The invention of claim 12 , wherein the integrated circuit further includes at least one field effect transistor having a conductive aligned supplemental gate.
21. The invention of claim 12 , wherein the integrated circuit further includes a redistribution layer and at least one additional capacitor and/or inductor formed from a portion of the at least one metal interconnect layer and a portion of the redistribution layer.
22. The invention of claim 12 , wherein the integrated circuit further includes at least one inductor formed from a portion of the at least one metal interconnect layer.