Interdigital capacitor
A routable lead frame (RLF) substrate has a conductive layer having first- and second-side traces having first fingers and second fingers, respectively, which are interdigitated with each other. A via layer is over the conductive layer. A first-side conductive via of the via layer is conductively coupled to the first-side trace. A second-side conductive via of the via layer is conductively coupled to the second-side trace. Dielectric molding material is disposed between the interdigitated fingers of the conductive layer and between the first-side conductive via and the second-side conductive via. The fingers and vias form an interdigital capacitor (IDC) useful in impedance matching and filtering.
1 . A substrate, comprising:
a conductive layer having a first trace comprising first fingers and a second trace comprising second fingers, the first fingers interdigitated with the second fingers;
a via layer over the conductive layer, the via layer comprising a first conductive via conductively coupled to the first trace and a second conductive via conductively coupled to the second trace;
dielectric material disposed between the first trace and the second trace and between the first conductive via and the second conductive via; and
a first terminal conductively coupled to the first trace,
wherein the first conductive via comprises a comb shape and the first terminal does not comprise a comb shape.
2 . The substrate of claim 1 , wherein the conductive layer and the via layer comprise copper, and the dielectric material comprises Ajinomoto Build-up Film (ABF).
3 . The substrate of claim 1 , wherein the conductive layer is a first conductive layer, the via layer is a first via layer, and the dielectric material is first dielectric material, the substrate further comprising:
a second conductive layer having a third trace comprising third fingers and a fourth trace comprising fourth fingers, the third fingers interdigitated with the fourth fingers, the third trace disposed over and conductively coupled to the first conductive via, the fourth trace disposed over and conductively coupled to the second conductive via;
a second via layer over the second conductive layer, a third conductive via of the second via layer conductively coupled to the third trace, a fourth conductive via of the second via layer conductively coupled to the fourth trace; and
second dielectric material disposed between the third trace and the fourth trace and between the third conductive via and the fourth conductive via.
4 . The substrate of claim 3 , wherein:
the first conductive via comprises fifth fingers,
the second conductive via comprises sixth fingers,
a finger of the third fingers is over and in conductive contact with a respective finger of the first fingers via a respective finger of the fifth fingers, and
a finger of the fourth fingers is over and in conductive contact with a respective finger of the second fingers via a respective finger of the sixth fingers.
5 . The substrate of claim 3 , further comprising:
a third conductive layer having a fifth trace comprising fifth fingers and a sixth trace comprising sixth fingers, the fifth fingers interdigitated with the sixth fingers, the fifth trace disposed over and conductively coupled to the third conductive via, the sixth trace disposed over and conductively coupled to the fourth conductive via; and
third dielectric material disposed between the fifth trace and the sixth trace.
6 . The substrate of claim 5 , wherein:
the third conductive via comprises seventh fingers,
the fourth conductive via comprises eighth fingers,
a finger of the fifth fingers is over and in conductive contact with a respective finger of the third fingers via a respective finger of the seventh fingers, and
a finger of the sixth fingers is over and in conductive contact with a respective finger of the fourth fingers via a respective finger of the eighth fingers.
7 . The substrate of claim 5 , further comprising:
a third via layer over the third conductive layer, the third via layer comprising a fifth conductive via and a sixth conductive via, the fifth conductive via conductively coupled to the fifth trace, the sixth conductive via conductively coupled to the sixth trace.
8 . The substrate of claim 7 , wherein the third dielectric material is also disposed between the fifth conductive via and the sixth conductive via.
9 . The substrate of claim 7 , wherein the third via layer extends above, and is entirely unencapsulated by the third dielectric material.
10 . An integrated circuit (IC), comprising:
a substrate;
an IC die attached and conductively coupled to an upper surface of the substrate; and
a mold encapsulating the IC die and the upper surface of the substrate, wherein the substrate comprises:
a conductive layer having a first trace comprising first fingers and a second trace comprising second fingers, the first fingers interdigitated with the second fingers;
a via layer over the conductive layer, the via layer comprising a first conductive via conductively coupled to the first trace and a second conductive via conductively coupled to the second trace;
dielectric material disposed between the first trace and the second trace and between the first conductive via and the second conductive via; and
a first terminal conductively coupled to the first trace,
wherein the first conductive via comprises a comb shape and the first terminal does not comprise a comb shape.
11 . The IC of claim 10 , wherein the substrate further comprises:
a second conductive layer having a third trace comprising third fingers and a fourth trace comprising fourth fingers, the third fingers interdigitated with the fourth fingers, the third trace disposed over and conductively coupled to the first conductive via, the fourth trace disposed over and conductively coupled to the second conductive via.
12 . The IC of claim 11 , wherein the substrate further comprises:
a third conductive layer having a fifth trace comprising fifth fingers and a sixth trace comprising sixth fingers, the fifth fingers interdigitated with the sixth fingers; and
a second via layer disposed between the second conductive layer and the third conductive layer, the second via layer comprising:
a third conductive via conductively coupling the third trace with the fifth trace; and
a fourth conductive via conductively coupling the fourth trace with the sixth trace.
13 . The IC of claim 10 , wherein the conductive layer and the via layer comprise copper, and the dielectric material comprises Ajinomoto Build-up Film (ABF).
14 . The IC of claim 12 , wherein the substrate further comprises:
a third via layer over the third conductive layer, the third via layer comprising a fifth conductive via and a sixth conductive via, the fifth conductive via conductively coupled to the fifth trace, the sixth conductive via conductively coupled to the sixth trace.
15 . The IC of claim 14 , wherein the third via layer extends above, and is entirely unencapsulated by the dielectric material.